From: Jiang Yunhong <yunhong.jiang@xxxxxxxxx>
Signed-off-by: Jiang Yunhong <yunhong.jiang@xxxxxxxxx>
Signed-off-by: Shan Haitao <haitao.shan@xxxxxxxxx>
Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx>
---
Makefile.target | 1 +
hw/apic-msidef.h | 2 +
hw/xen_pci_passthrough.h | 20 ++
hw/xen_pci_passthrough_msi.c | 667 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 690 insertions(+), 0 deletions(-)
create mode 100644 hw/xen_pci_passthrough_msi.c
diff --git a/Makefile.target b/Makefile.target
index 875a507..76530d9 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -213,6 +213,7 @@ obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += host-pci-device.o
obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough.o
obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_helpers.o
obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_config_init.o
+obj-i386-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pci_passthrough_msi.o
# Inter-VM PCI shared memory
CONFIG_IVSHMEM =
diff --git a/hw/apic-msidef.h b/hw/apic-msidef.h
index 3182f0b..6e2eb71 100644
--- a/hw/apic-msidef.h
+++ b/hw/apic-msidef.h
@@ -22,6 +22,8 @@
#define MSI_ADDR_DEST_MODE_SHIFT 2
+#define MSI_ADDR_REDIRECTION_SHIFT 3
+
#define MSI_ADDR_DEST_ID_SHIFT 12
#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
diff --git a/hw/xen_pci_passthrough.h b/hw/xen_pci_passthrough.h
index 7cb563f..5f404b0 100644
--- a/hw/xen_pci_passthrough.h
+++ b/hw/xen_pci_passthrough.h
@@ -63,6 +63,10 @@ typedef int (*conf_byte_restore)
#define PT_BAR_ALLF 0xFFFFFFFF /* BAR ALLF value */
+/* MSI-X */
+#define PT_MSI_FLAG_UNINIT 0x1000
+#define PT_MSI_FLAG_MAPPED 0x2000
+
typedef enum {
GRP_TYPE_HARDWIRED = 0, /* 0 Hardwired reg group */
@@ -257,4 +261,20 @@ static inline uint8_t pci_read_intx(XenPCIPassthroughState
*s)
}
uint8_t pci_intx(XenPCIPassthroughState *ptdev);
+/* MSI/MSI-X */
+void pt_msi_set_enable(XenPCIPassthroughState *s, int en);
+int pt_msi_setup(XenPCIPassthroughState *s);
+int pt_msi_update(XenPCIPassthroughState *d);
+void pt_msi_disable(XenPCIPassthroughState *s);
+int pt_enable_msi_translate(XenPCIPassthroughState *s);
+void pt_disable_msi_translate(XenPCIPassthroughState *s);
+
+int pt_msix_init(XenPCIPassthroughState *s, int pos);
+void pt_msix_delete(XenPCIPassthroughState *s);
+int pt_msix_update(XenPCIPassthroughState *s);
+int pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
+void pt_msix_disable(XenPCIPassthroughState *s);
+int pt_add_msix_mapping(XenPCIPassthroughState *s, int bar_index);
+int pt_remove_msix_mapping(XenPCIPassthroughState *s, int bar_index);
+
#endif /* !QEMU_HW_XEN_PCI_PASSTHROUGH_H */
diff --git a/hw/xen_pci_passthrough_msi.c b/hw/xen_pci_passthrough_msi.c
new file mode 100644
index 0000000..533aef4
--- /dev/null
+++ b/hw/xen_pci_passthrough_msi.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2007, Intel Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Jiang Yunhong <yunhong.jiang@xxxxxxxxx>
+ *
+ * This file implements direct PCI assignment to a HVM guest
+ */
+
+#include <sys/mman.h>
+
+#include "xen_backend.h"
+#include "xen_pci_passthrough.h"
+#include "apic-msidef.h"
+
+
+#define AUTO_ASSIGN -1
+
+/* shift count for gflags */
+#define GFLAGS_SHIFT_DEST_ID 0
+#define GFLAGS_SHIFT_RH 8
+#define GFLAGS_SHIFT_DM 9
+#define GLFAGS_SHIFT_DELIV_MODE 12
+#define GLFAGS_SHIFT_TRG_MODE 15
+
+
+void pt_msi_set_enable(XenPCIPassthroughState *s, int en)
+{
+ uint16_t val = 0;
+ uint32_t address = 0;
+ PT_LOG("enable: %i\n", en);
+
+ if (!s->msi) {
+ return;
+ }
+
+ address = s->msi->ctrl_offset;
+ if (!address) {
+ return;
+ }
+
+ val = host_pci_get_word(s->real_device, address);
+ val &= ~PCI_MSI_FLAGS_ENABLE;
+ val |= en & PCI_MSI_FLAGS_ENABLE;
+ host_pci_set_word(s->real_device, address, val);
+
+ PT_LOG("done, address: %#x, val: %#x\n", address, val);
+}
+
+static void msix_set_enable(XenPCIPassthroughState *s, int en)
+{
+ uint16_t val = 0;
+ uint32_t address = 0;
+
+ if (!s->msix) {
+ return;
+ }
+
+ address = s->msix->ctrl_offset;
+ if (!address) {
+ return;
+ }
+
+ val = host_pci_get_word(s->real_device, address);
+ val &= ~PCI_MSIX_FLAGS_ENABLE;
+ if (en) {
+ val |= PCI_MSIX_FLAGS_ENABLE;
+ }
+ host_pci_set_word(s->real_device, address, val);
+}
+
+/*********************************/
+/* MSI virtuailization functions */
+
+/*
+ * setup physical msi, but didn't enable it
+ */
+int pt_msi_setup(XenPCIPassthroughState *s)
+{
+ int pirq = -1;
+ uint8_t gvec = 0;
+
+ if (!(s->msi->flags & PT_MSI_FLAG_UNINIT)) {
+ PT_LOG("Error: setup physical after initialized??\n");
+ return -1;
+ }
+
+ gvec = s->msi->data & 0xFF;
+ if (!gvec) {
+ /* if gvec is 0, the guest is asking for a particular pirq that
+ * is passed as dest_id */
+ pirq = (s->msi->addr_hi & 0xffffff00) |
+ ((s->msi->addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
+ if (!pirq) {
+ /* this probably identifies an misconfiguration of the guest,
+ * try the emulated path */
+ pirq = -1;
+ } else {
+ PT_LOG("pt_msi_setup requested pirq = %d\n", pirq);
+ }
+ }
+
+ if (xc_physdev_map_pirq_msi(xen_xc, xen_domid, AUTO_ASSIGN, &pirq,
+ PCI_DEVFN(s->real_device->dev,
+ s->real_device->func),
+ s->real_device->bus, 0, 0)) {
+ PT_LOG("Error: Mapping of MSI failed.\n");
+ return -1;
+ }
+
+ if (pirq < 0) {
+ PT_LOG("Error: Invalid pirq number\n");
+ return -1;
+ }
+
+ s->msi->pirq = pirq;
+ PT_LOG("msi mapped with pirq %x\n", pirq);
+
+ return 0;
+}
+
+static uint32_t __get_msi_gflags(uint32_t data, uint64_t addr)
+{
+ uint32_t result = 0;
+ int rh, dm, dest_id, deliv_mode, trig_mode;
+
+ rh = (addr >> MSI_ADDR_REDIRECTION_SHIFT) & 0x1;
+ dm = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
+ dest_id = (addr >> MSI_ADDR_DEST_ID_SHIFT) & 0xff;
+ deliv_mode = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
+ trig_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
+
+ result = dest_id | (rh << GFLAGS_SHIFT_RH) | (dm << GFLAGS_SHIFT_DM) |
+ (deliv_mode << GLFAGS_SHIFT_DELIV_MODE) |
+ (trig_mode << GLFAGS_SHIFT_TRG_MODE);
+
+ return result;
+}
+
+int pt_msi_update(XenPCIPassthroughState *s)
+{
+ uint8_t gvec = 0;
+ uint32_t gflags = 0;
+ uint64_t addr = 0;
+ int ret = 0;
+
+ /* get vector, address, flags info, etc. */
+ gvec = s->msi->data & 0xFF;
+ addr = (uint64_t)s->msi->addr_hi << 32 | s->msi->addr_lo;
+ gflags = __get_msi_gflags(s->msi->data, addr);
+
+ PT_LOG("Update msi with pirq %x gvec %x gflags %x\n",
+ s->msi->pirq, gvec, gflags);
+
+ ret = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec,
+ s->msi->pirq, gflags, 0);
+
+ if (ret) {
+ PT_LOG("Error: Binding of MSI failed.\n");
+
+ if (xc_physdev_unmap_pirq(xen_xc, xen_domid, s->msi->pirq)) {
+ PT_LOG("Error: Unmapping of MSI failed.\n");
+ }
+ s->msi->pirq = -1;
+ return ret;
+ }
+ return 0;
+}
+
+void pt_msi_disable(XenPCIPassthroughState *s)
+{
+ PCIDevice *d = &s->dev;
+ uint8_t gvec = 0;
+ uint32_t gflags = 0;
+ uint64_t addr = 0;
+ uint8_t e_device = 0;
+ uint8_t e_intx = 0;
+
+ pt_msi_set_enable(s, 0);
+
+ e_device = PCI_SLOT(d->devfn);
+ e_intx = pci_intx(s);
+
+ if (s->msi_trans_en) {
+ if (xc_domain_unbind_pt_irq(xen_xc, xen_domid, s->msi->pirq,
+ PT_IRQ_TYPE_MSI_TRANSLATE, 0,
+ e_device, e_intx, 0)) {
+ PT_LOG("Error: Unbinding pt irq for MSI-INTx failed!\n");
+ goto out;
+ }
+ } else if (!(s->msi->flags & PT_MSI_FLAG_UNINIT)) {
+ /* get vector, address, flags info, etc. */
+ gvec = s->msi->data & 0xFF;
+ addr = (uint64_t)s->msi->addr_hi << 32 | s->msi->addr_lo;
+ gflags = __get_msi_gflags(s->msi->data, addr);
+
+ PT_LOG("Unbind msi with pirq %x, gvec %x\n",
+ s->msi->pirq, gvec);
+
+ if (xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec,
+ s->msi->pirq, gflags)) {
+ PT_LOG("Error: Unbinding of MSI failed. [%02x:%02x.%x]\n",
+ pci_bus_num(d->bus), PCI_SLOT(d->devfn),
+ PCI_FUNC(d->devfn));
+ goto out;
+ }
+ }
+
+ if (s->msi->pirq != -1) {
+ PT_LOG("Unmap msi with pirq %x\n", s->msi->pirq);
+
+ if (xc_physdev_unmap_pirq(xen_xc, xen_domid, s->msi->pirq)) {
+ PT_LOG("Error: Unmapping of MSI failed. [%02x:%02x.%x]\n",
+ pci_bus_num(d->bus), PCI_SLOT(d->devfn),
+ PCI_FUNC(d->devfn));
+ goto out;
+ }
+ }
+
+out:
+ /* clear msi info */
+ s->msi->flags = 0;
+ s->msi->pirq = -1;
+ s->msi_trans_en = 0;
+}
+
+/* MSI-INTx translation virtulization functions */
+int pt_enable_msi_translate(XenPCIPassthroughState *s)
+{
+ uint8_t e_device = 0;
+ uint8_t e_intx = 0;
+
+ if (!(s->msi && s->msi_trans_cap)) {
+ return -1;
+ }
+
+ pt_msi_set_enable(s, 0);
+ s->msi_trans_en = 0;
+
+ if (pt_msi_setup(s)) {
+ PT_LOG("Error: MSI-INTx translation MSI setup failed, fallback\n");
+ return -1;
+ }
+
+ e_device = PCI_SLOT(s->dev.devfn);
+ /* fix virtual interrupt pin to INTA# */
+ e_intx = pci_intx(s);
+
+ if (xc_domain_bind_pt_irq(xen_xc, xen_domid, s->msi->pirq,
+ PT_IRQ_TYPE_MSI_TRANSLATE, 0,
+ e_device, e_intx, 0)) {
+ PT_LOG("Error: MSI-INTx translation bind failed, fallback\n");
+
+ if (xc_physdev_unmap_pirq(xen_xc, xen_domid, s->msi->pirq)) {
+ PT_LOG("Error: Unmapping of MSI failed.\n");
+ }
+ s->msi->pirq = -1;
+ return -1;
+ }
+
+ pt_msi_set_enable(s, 1);
+ s->msi_trans_en = 1;
+
+ return 0;
+}
+
+void pt_disable_msi_translate(XenPCIPassthroughState *s)
+{
+ uint8_t e_device = 0;
+ uint8_t e_intx = 0;
+
+ /* MSI_ENABLE bit should be disabed until the new handler is set */
+ pt_msi_set_enable(s, 0);
+
+ e_device = PCI_SLOT(s->dev.devfn);
+ e_intx = pci_intx(s);
+
+ if (xc_domain_unbind_pt_irq(xen_xc, xen_domid, s->msi->pirq,
+ PT_IRQ_TYPE_MSI_TRANSLATE, 0,
+ e_device, e_intx, 0)) {
+ PT_LOG("Error: Unbinding pt irq for MSI-INTx failed!\n");
+ }
+
+ if (s->machine_irq) {
+ if (xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, s->machine_irq,
+ 0, e_device, e_intx)) {
+ PT_LOG("Error: Rebinding of interrupt failed!\n");
+ }
+ }
+
+ s->msi_trans_en = 0;
+}
+
+/*********************************/
+/* MSI-X virtulization functions */
+
+static void mask_physical_msix_entry(XenPCIPassthroughState *s,
+ int entry_nr, int mask)
+{
+ void *phys_off;
+
+ phys_off = s->msix->phys_iomem_base + 16 * entry_nr + 12;
+ *(uint32_t *)phys_off = mask;
+}
+
+static int pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr)
+{
+ XenMSIXEntry *entry = &s->msix->msix_entry[entry_nr];
+ int pirq = entry->pirq;
+ int gvec = entry->io_mem[2] & 0xff;
+ uint64_t gaddr = *(uint64_t *)&entry->io_mem[0];
+ uint32_t gflags = __get_msi_gflags(entry->io_mem[2], gaddr);
+ int ret;
+
+ if (!entry->flags) {
+ return 0;
+ }
+
+ if (!gvec) {
+ /* if gvec is 0, the guest is asking for a particular pirq that
+ * is passed as dest_id */
+ pirq = ((gaddr >> 32) & 0xffffff00) |
+ (((gaddr & 0xffffffff) >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
+ if (!pirq) {
+ /* this probably identifies an misconfiguration of the guest,
+ * try the emulated path */
+ pirq = -1;
+ } else {
+ PT_LOG("pt_msix_update_one requested pirq = %d\n", pirq);
+ }
+ }
+
+ /* Check if this entry is already mapped */
+ if (entry->pirq == -1) {
+ ret = xc_physdev_map_pirq_msi(xen_xc, xen_domid, AUTO_ASSIGN, &pirq,
+ PCI_DEVFN(s->real_device->dev,
+ s->real_device->func),
+ s->real_device->bus, entry_nr,
+ s->msix->table_base);
+ if (ret) {
+ PT_LOG("Error: Mapping msix entry %x\n", entry_nr);
+ return ret;
+ }
+ entry->pirq = pirq;
+ }
+
+ PT_LOG("Update msix entry %x with pirq %x gvec %x\n",
+ entry_nr, pirq, gvec);
+
+ ret = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, pirq, gflags,
+ s->msix->mmio_base_addr);
+ if (ret) {
+ PT_LOG("Error: Updating msix irq info for entry %d\n", entry_nr);
+
+ if (xc_physdev_unmap_pirq(xen_xc, xen_domid, entry->pirq)) {
+ PT_LOG("Error: Unmapping of MSI-X failed.\n");
+ }
+ entry->pirq = -1;
+ return ret;
+ }
+
+ entry->flags = 0;
+
+ return 0;
+}
+
+int pt_msix_update(XenPCIPassthroughState *s)
+{
+ XenPTMSIX *msix = s->msix;
+ int i;
+
+ for (i = 0; i < msix->total_entries; i++) {
+ pt_msix_update_one(s, i);
+ }
+
+ return 0;
+}
+
+void pt_msix_disable(XenPCIPassthroughState *s)
+{
+ PCIDevice *d = &s->dev;
+ uint8_t gvec = 0;
+ uint32_t gflags = 0;
+ uint64_t addr = 0;
+ int i = 0;
+ XenMSIXEntry *entry = NULL;
+
+ msix_set_enable(s, 0);
+
+ for (i = 0; i < s->msix->total_entries; i++) {
+ entry = &s->msix->msix_entry[i];
+
+ if (entry->pirq == -1) {
+ continue;
+ }
+
+ gvec = entry->io_mem[2] & 0xff;
+ addr = *(uint64_t *)&entry->io_mem[0];
+ gflags = __get_msi_gflags(entry->io_mem[2], addr);
+
+ PT_LOG("Unbind msix with pirq %x, gvec %x\n",
+ entry->pirq, gvec);
+
+ if (xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec,
+ entry->pirq, gflags)) {
+ PT_LOG("Error: Unbinding of MSI-X failed. [%02x:%02x.%x]\n",
+ pci_bus_num(d->bus), PCI_SLOT(d->devfn),
+ PCI_FUNC(d->devfn));
+ } else {
+ PT_LOG("Unmap msix with pirq %x\n", entry->pirq);
+
+ if (xc_physdev_unmap_pirq(xen_xc, xen_domid, entry->pirq)) {
+ PT_LOG("Error: Unmapping of MSI-X failed. [%02x:%02x.%x]\n",
+ pci_bus_num(d->bus),
+ PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
+ }
+ }
+ /* clear msi-x info */
+ entry->pirq = -1;
+ entry->flags = 0;
+ }
+}
+
+int pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index)
+{
+ XenMSIXEntry *entry;
+ int i, ret;
+
+ if (!(s->msix && s->msix->bar_index == bar_index)) {
+ return 0;
+ }
+
+ for (i = 0; i < s->msix->total_entries; i++) {
+ entry = &s->msix->msix_entry[i];
+ if (entry->pirq != -1) {
+ ret = xc_domain_unbind_pt_irq(xen_xc, xen_domid, entry->pirq,
+ PT_IRQ_TYPE_MSI, 0, 0, 0, 0);
+ if (ret) {
+ PT_LOG("Error: unbind MSI-X entry %d failed\n", entry->pirq);
+ }
+ entry->flags = 1;
+ }
+ }
+ pt_msix_update(s);
+
+ return 0;
+}
+
+static void pci_msix_invalid_write(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ PT_LOG("Error: Invalid write to MSI-X table,"
+ " only dword access is allowed.\n");
+}
+
+static void pci_msix_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ XenPCIPassthroughState *s = (XenPCIPassthroughState *)opaque;
+ XenPTMSIX *msix = s->msix;
+ XenMSIXEntry *entry;
+ int entry_nr, offset;
+ void *phys_off;
+ uint32_t vec_ctrl;
+
+ if (addr % 4) {
+ PT_LOG("Error: Unaligned dword access to MSI-X table, "
+ "addr %016"PRIx64"\n", addr);
+ return;
+ }
+
+ PT_LOG("addr: "TARGET_FMT_plx", val: %#x\n", addr, val);
+
+ entry_nr = addr / 16;
+ entry = &msix->msix_entry[entry_nr];
+ offset = (addr % 16) / 4;
+
+ /*
+ * If Xen intercepts the mask bit access, io_mem[3] may not be
+ * up-to-date. Read from hardware directly.
+ */
+ phys_off = s->msix->phys_iomem_base + 16 * entry_nr + 12;
+ vec_ctrl = *(uint32_t *)phys_off;
+
+ if (offset != 3 && msix->enabled && !(vec_ctrl & 0x1)) {
+ PT_LOG("Error: Can't update msix entry %d since MSI-X is already "
+ "function.\n", entry_nr);
+ return;
+ }
+
+ if (offset != 3 && entry->io_mem[offset] != val) {
+ entry->flags = 1;
+ }
+ entry->io_mem[offset] = val;
+
+ if (offset == 3) {
+ if (msix->enabled && !(val & 0x1)) {
+ pt_msix_update_one(s, entry_nr);
+ }
+ mask_physical_msix_entry(s, entry_nr, entry->io_mem[3] & 0x1);
+ }
+}
+
+static CPUWriteMemoryFunc *pci_msix_write[] = {
+ pci_msix_invalid_write,
+ pci_msix_invalid_write,
+ pci_msix_writel
+};
+
+static uint32_t pci_msix_invalid_read(void *opaque, target_phys_addr_t addr)
+{
+ PT_LOG("Error: Invalid read to MSI-X table,"
+ " only dword access is allowed.\n");
+ return 0;
+}
+
+static uint32_t pci_msix_readl(void *opaque, target_phys_addr_t addr)
+{
+ XenPCIPassthroughState *s = (XenPCIPassthroughState *)opaque;
+ XenPTMSIX *msix = s->msix;
+ int entry_nr, offset;
+
+ if (addr % 4) {
+ PT_LOG("Error: Unaligned dword access to MSI-X table, "
+ "addr %016"PRIx64"\n", addr);
+ return 0;
+ }
+
+ PT_LOG("addr: "TARGET_FMT_plx"\n", addr);
+
+ entry_nr = addr / 16;
+ offset = (addr % 16) / 4;
+
+ return msix->msix_entry[entry_nr].io_mem[offset];
+}
+
+static CPUReadMemoryFunc *pci_msix_read[] = {
+ pci_msix_invalid_read,
+ pci_msix_invalid_read,
+ pci_msix_readl
+};
+
+int pt_add_msix_mapping(XenPCIPassthroughState *s, int bar_index)
+{
+ if (!(s->msix && s->msix->bar_index == bar_index)) {
+ return 0;
+ }
+
+ return xc_domain_memory_mapping(xen_xc, xen_domid,
+ s->msix->mmio_base_addr >> XC_PAGE_SHIFT,
+ (s->bases[bar_index].access.maddr + s->msix->table_off)
+ >> XC_PAGE_SHIFT,
+ (s->msix->total_entries * 16 + XC_PAGE_SIZE - 1) >> XC_PAGE_SHIFT,
+ DPCI_ADD_MAPPING);
+}
+
+int pt_remove_msix_mapping(XenPCIPassthroughState *s, int bar_index)
+{
+ if (!(s->msix && s->msix->bar_index == bar_index)) {
+ return 0;
+ }
+
+ s->msix->mmio_base_addr = s->bases[bar_index].e_physbase
+ + s->msix->table_off;
+
+ cpu_register_physical_memory(s->msix->mmio_base_addr,
+ s->msix->total_entries * 16,
+ s->msix->mmio_index);
+
+ return xc_domain_memory_mapping(xen_xc, xen_domid,
+ s->msix->mmio_base_addr >> XC_PAGE_SHIFT,
+ (s->bases[bar_index].access.maddr + s->msix->table_off)
+ >> XC_PAGE_SHIFT,
+ (s->msix->total_entries * 16 + XC_PAGE_SIZE - 1) >> XC_PAGE_SHIFT,
+ DPCI_REMOVE_MAPPING);
+}
+
+int pt_msix_init(XenPCIPassthroughState *s, int base)
+{
+ uint8_t id;
+ uint16_t control;
+ int i, total_entries, table_off, bar_index;
+ HostPCIDevice *d = s->real_device;
+ int fd;
+
+ id = host_pci_get_byte(d, base + PCI_CAP_LIST_ID);
+
+ if (id != PCI_CAP_ID_MSIX) {
+ PT_LOG("Error: Invalid id %#x base %#x\n", id, base);
+ return -1;
+ }
+
+ control = host_pci_get_word(d, base + 2);
+ total_entries = control & 0x7ff;
+ total_entries += 1;
+
+ s->msix = g_malloc0(sizeof (XenPTMSIX)
+ + total_entries * sizeof (XenMSIXEntry));
+
+ s->msix->total_entries = total_entries;
+ for (i = 0; i < total_entries; i++) {
+ s->msix->msix_entry[i].pirq = -1;
+ }
+
+ s->msix->mmio_index =
+ cpu_register_io_memory(pci_msix_read, pci_msix_write,
+ s, DEVICE_NATIVE_ENDIAN);
+
+ table_off = host_pci_get_long(d, base + PCI_MSIX_TABLE);
+ bar_index = s->msix->bar_index = table_off & PCI_MSIX_FLAGS_BIRMASK;
+ table_off = s->msix->table_off = table_off & ~PCI_MSIX_FLAGS_BIRMASK;
+ s->msix->table_base = s->real_device->io_regions[bar_index].base_addr;
+ PT_LOG("get MSI-X table bar base %#"PRIx64"\n", s->msix->table_base);
+
+ fd = open("/dev/mem", O_RDWR);
+ if (fd == -1) {
+ PT_LOG("Error: Can't open /dev/mem: %s\n", strerror(errno));
+ goto error_out;
+ }
+ PT_LOG("table_off = %#x, total_entries = %d\n", table_off, total_entries);
+ s->msix->table_offset_adjust = table_off & 0x0fff;
+ s->msix->phys_iomem_base =
+ mmap(0,
+ total_entries * 16 + s->msix->table_offset_adjust,
+ PROT_WRITE | PROT_READ,
+ MAP_SHARED | MAP_LOCKED,
+ fd,
+ s->msix->table_base + table_off - s->msix->table_offset_adjust);
+
+ if (s->msix->phys_iomem_base == MAP_FAILED) {
+ PT_LOG("Error: Can't map physical MSI-X table: %s\n", strerror(errno));
+ close(fd);
+ goto error_out;
+ }
+ s->msix->phys_iomem_base = (char *)s->msix->phys_iomem_base
+ + s->msix->table_offset_adjust;
+
+ close(fd);
+
+ PT_LOG("mapping physical MSI-X table to %p\n", s->msix->phys_iomem_base);
+ return 0;
+
+error_out:
+ g_free(s->msix);
+ s->msix = NULL;
+ return -1;
+}
+
+void pt_msix_delete(XenPCIPassthroughState *s)
+{
+ /* unmap the MSI-X memory mapped register area */
+ if (s->msix->phys_iomem_base) {
+ PT_LOG("unmapping physical MSI-X table from %lx\n",
+ (unsigned long)s->msix->phys_iomem_base);
+ munmap(s->msix->phys_iomem_base, s->msix->total_entries * 16 +
+ s->msix->table_offset_adjust);
+ }
+
+ if (s->msix->mmio_index > 0) {
+ cpu_unregister_io_memory(s->msix->mmio_index);
+ }
+
+ g_free(s->msix);
+ s->msix = NULL;
+}
--
Anthony PERARD
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