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Re: [Xen-devel] [PATCH 0 of 3] Avoid sharing vectors within a device whe

To: George Dunlap <george.dunlap@xxxxxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: Re: [Xen-devel] [PATCH 0 of 3] Avoid sharing vectors within a device when using an AMD IOMMU
From: Keir Fraser <keir.xen@xxxxxxxxx>
Date: Tue, 26 Jul 2011 18:01:36 +0100
Cc: wei.wang2@xxxxxxx
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Thread-topic: [Xen-devel] [PATCH 0 of 3] Avoid sharing vectors within a device when using an AMD IOMMU
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On 26/07/2011 17:33, "George Dunlap" <george.dunlap@xxxxxxxxxxxxx> wrote:

> The interrupt remapping tables on AMD IOMMUs index by vector only.
> This means that if two MSIs go through the table that are destined for
> different cpus, but they share the same vector, they will be
> redirected to the same place.  (E.g., one interrupt on p5 vector 67,
> another interrupt on p7 vector 67; both will be redirected to the same
> place.)
> Introducing per-device interrupt mappings reduces the problem, but
> does not solve it completely if the same device can have multiple IRQs
> assigned to it, because you can get the same issue -- two different
> IRQs from the same device can be assigned the same vector on different
> cpus.  This causes one of the IRQs to activated when either interrupt
> is triggered, and the other IRQ to never receive any interrupts.

The patches look fine, but I don't see a reason to add yet more command-line
options. AMD systems using irq remapping will need to avoid vector sharing;
other systems do not need to do so. We detect that automatically and DTRT
and there's no reason for a user to override that. It's just extending the
set of arcane IOMMU command line settings that noone will understand the
implications of specifying.

 -- Keir

> This series consists of three patches:
> 1: Introduce infrastructure to allow irqs to share vector maps.  Any
> IRQs sharing the same vector map will never have vector collisions.
> 2: Introduce option to have per-device vector maps for MSI IRQs.
> 3: Automatically enable per-device vector maps when running on an AMD
> system with the IOMMU enabled, unless otherwise specified.
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