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[Xen-devel] Questions about ept
| To: | xen-devel@xxxxxxxxxxxxxxxxxxx |
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| Subject: | [Xen-devel] Questions about ept |
| From: | YAO <yffbrave@xxxxxxxxx> |
| Date: | Thu, 9 Jun 2011 15:52:52 +0800 |
| Delivery-date: | Thu, 09 Jun 2011 00:53:30 -0700 |
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Hi, I've been reading the code in xen/arch/x86/mm/hap and got some questions: 1. Are they the support for intel ept? If so, where is the support for amd rvi? 2. I read the intel manual, it says EPT paging is similar to IA-32e mode which has 4 level page. So, if the xen is running under 32bit PAE mode, is the ept paging still 4 levels?
by the way, is dom0 always 32bit pae? 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly), what's the relationship between them? why do we need p2m when we use hap?
4.Can I use ept to control access to some of the guest pages? Thanks.
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