[Xen-devel] Re: [PATCH 1/2] apic: Move hypervisor detection of x2apic to hypervisor.h

[Sheng Yang <sheng@xxxxxxxxxxxxxxx>]

On Wednesday 08 December 2010 14:03:59 Sheng Yang wrote:
> Signed-off-by: Sheng Yang <sheng@xxxxxxxxxxxxxxx>
> ---

Jeremy?

--
regards
Yang, Sheng

>  arch/x86/include/asm/hypervisor.h |    9 +++++++++
>  arch/x86/kernel/apic/apic.c       |    5 +++--
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/include/asm/hypervisor.h
> b/arch/x86/include/asm/hypervisor.h index ff2546c..0c6f7af 100644
> --- a/arch/x86/include/asm/hypervisor.h
> +++ b/arch/x86/include/asm/hypervisor.h
> @@ -20,6 +20,8 @@
>  #ifndef _ASM_X86_HYPERVISOR_H
>  #define _ASM_X86_HYPERVISOR_H
> 
> +#include <asm/kvm_para.h>
> +
>  extern void init_hypervisor(struct cpuinfo_x86 *c);
>  extern void init_hypervisor_platform(void);
> 
> @@ -47,4 +49,11 @@ extern const struct hypervisor_x86 x86_hyper_vmware;
>  extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
>  extern const struct hypervisor_x86 x86_hyper_xen_hvm;
> 
> +static inline bool hypervisor_x2apic_available(void)
> +{
> +     if (kvm_para_available())
> +             return true;
> +     return false;
> +}
> +
>  #endif
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index 3f838d5..8408f2d 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -50,8 +50,8 @@
>  #include <asm/mtrr.h>
>  #include <asm/smp.h>
>  #include <asm/mce.h>
> -#include <asm/kvm_para.h>
>  #include <asm/tsc.h>
> +#include <asm/hypervisor.h>
> 
>  unsigned int num_processors;
> 
> @@ -1476,7 +1476,8 @@ void __init enable_IR_x2apic(void)
>               /* IR is required if there is APIC ID > 255 even when running
>                * under KVM
>                */
> -             if (max_physical_apicid > 255 || !kvm_para_available())
> +             if (max_physical_apicid > 255 ||
> +                 !hypervisor_x2apic_available())
>                       goto nox2apic;
>               /*
>                * without IR all CPUs can be addressed by IOAPIC/MSI

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