Hi Allen,
Actually, each amd iommu pde entry uses bit 9-11 to encode next page table
level, but these bits are also used as AVL bits by p2m table to encode
different page types...So, it might not be quite easy to share NPT table with
amd iommu unless we change p2m table encoding for this first.
Thanks,
Wei
On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote:
> Hi Wei,
>
> My understanding is that both EPT/NPT already supports 2M and 1G page
> sizes. If this is true and if NPT supports the same page table format as
> AMD iommu, shouldn't iommu 2M and 1G support just a matter of pointing
> iommu page table pointer to NPT page table of the same guest OS thus
> sharing the same page table between NPT and AMD iommu?
>
> This should save a lot code changes in iommu code. We just need to flush
> iommu page table in IOTLB at appropriate places.
>
> Allen
>
> -----Original Message-----
> From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
> [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Wei Wang2 Sent:
> Friday, December 03, 2010 8:04 AM
> To: xen-devel@xxxxxxxxxxxxxxxxxxx
> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support -
> implementation
>
> This is the implementation.
>
> Thanks,
> We
> Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
> --
> Legal Information:
> Advanced Micro Devices GmbH
> Sitz: Dornach, Gemeinde Aschheim,
> Landkreis München Registergericht München, HRB Nr. 43632
> Geschäftsführer:
> Alberto Bozzo, Andrew Bowd
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