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[Xen-devel] Re: ATA driver failures with pvops dom0, (was: aic79xx failu

To: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
Subject: [Xen-devel] Re: ATA driver failures with pvops dom0, (was: aic79xx failures with pvops dom0
From: Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>
Date: Tue, 23 Nov 2010 17:43:22 +0000
Cc: micah anderson <micah@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <Stefano.Stabellini@xxxxxxxxxxxxx>
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On Mon, 22 Nov 2010, Konrad Rzeszutek Wilk wrote:
> > [    0.000000] MPTABLE: OEM ID:  
> > [    0.000000] MPTABLE: Product ID: Kings Canyon
> > [    0.000000] MPTABLE: APIC at: 0xFEE00000
> Oh, MPTtable..
> .. snip ..
> > [    1.560006] ACPI: Interpreter disabled.
> .. and ACPI disable..
> ..

This configuration cannot work properly because the kernel is going to
try to setup the three ioapics writing to their MMIO regions, and that
is going to silently fail because under Xen we are mapping a dummy page
In fact the kernel is not allowed to configure the ioapics directly, it
is supposed to ask Xen to do it using the PHYSDEVOP_setup_gsi hypercall,
implemented in xen_register_gsi.
However xen_register_gsi is only called from acpi_register_gsi, so it is
only going to work if ACPI is enabled; this is why CONFIG_XEN_DOM0
depends on CONFIG_ACPI in the 2.6.37 kernel.

Another reason why it is not going to work is that dom0 needs to remap
all the GSIs/MSIs into pirqs to be able to receive event notifications.
This is done by xen_register_pirq that is called automatically for all
the legacy irqs and by xen_register_gsi. So without ACPI dom0 wouldn't
remap any gsi > 16.

> > [    1.908022] pci 0000:00:1f.0: PIIX/ICH IRQ router [8086:2480]
> and using the southbridge to program the IRQs.
> This looks like the old PIIX4 controller, which is what QEMU uses.
> Stefano, do you remember how the IRQs are programmed in QEMU
> with this? Is the OS writting in the config space of the southbridge
> (IRQ router) the vector values that correspond to the IOAPIC? So instead
> of poking at the IOAPIC it does it directly in the IRQ router. And it would
> use the MPtable for something - thought I don't remember what.

A write to the pci config space of the piix chipset would modify the
link routes, like INT A -> IRQ 28 in the example below.

> ... snip..
> > [    6.117107] querying PCI -> IRQ mapping bus:3, slot:2, pin:0.
> > [    6.117117] IOAPIC[1]: Set routing entry (3-4 -> 0x69 -> IRQ 28 Mode:1 
> > Active:1)
> > [    6.117124] aic79xx 0000:03:02.0: PCI->APIC IRQ transform: INT A -> IRQ 
> > 28
> and sure enough it looks to looking in the MPtable for the pin value
> and the writing in the IRQ router the vector value.

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