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Re: [Xen-devel] How EPT translates an X86_32 guest physical address?

To: Chu Rui <ruichu@xxxxxxxxx>, Ian Campbell <Ian.Campbell@xxxxxxxxxxxxx>
Subject: Re: [Xen-devel] How EPT translates an X86_32 guest physical address?
From: Keir Fraser <keir@xxxxxxx>
Date: Wed, 17 Nov 2010 12:02:09 +0000
Cc: George Dunlap <George.Dunlap@xxxxxxxxxxxxx>, "Xen-devel@xxxxxxxxxxxxxxxxxxx" <Xen-devel@xxxxxxxxxxxxxxxxxxx>, Superymk <superymkxen@xxxxxxxxxxx>
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Thread-topic: [Xen-devel] How EPT translates an X86_32 guest physical address?
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32-bit hypervisor does not support 64-bit guests.

On 17/11/2010 11:57, "Chu Rui" <ruichu@xxxxxxxxx> wrote:

> Sorry, perhaps I am confused. If the VMM works on the tranditional protect
> mode with 2-level addressing, what will happen when the guest "thinks" it is
> working in the x86-64 mode with 4-level addressing?
> 2010/11/17 Ian Campbell <Ian.Campbell@xxxxxxxxxxxxx>
>> On Wed, 2010-11-17 at 11:26 +0000, Chu Rui wrote:
>>> Okay, in my mind, the hardware has only one work mode, 32bit or 64bit.
>>> Thus the 32bit guest address will be extended under the 64bit host.
>>> But what will happen for a 64bit guest under a 32bit host :-)
>> You appear to be confusing virtual address size, which is 32 or 64 bit
>> depending on mode, with phsyical address size, which depends on the
>> particular CPU model etc and not the mode it is running in.
>> CPUs these days typically support physical address sizes of something
>> like 44 or 46 bits, even if they are running in 64 bit mode.
>> Ian.
>>> 2010/11/17 Ian Campbell <Ian.Campbell@xxxxxxxxxx>
>>>         On Wed, 2010-11-17 at 10:32 +0000, George Dunlap wrote:
>>>         > The exact implementation of 32-bit mode on a 64-bit capable
>>>         processor
>>>         > is something only the engineers at Intel know; but logically
>>>         yes,
>>>         > whatever it does is equivalent to first zero-extending the
>>>         32-bit
>>>         > value.
>>>         Even on x86_32 physical addresses are >32 bit (think PAE). cr3
>>>         is a
>>>         physical address, even if the register which exposes it
>>>         happens to be
>>>         limited to 32 bits. cr3 has probably already been expanded to
>>>         a full
>>>         physical address by the time EPT sees it and I don't think
>>>         there's any
>>>         difference between 32 and 64 bit (at least in this aspect) in
>>>         how EPT
>>>         handles the translation from physical address to machine
>>>         address.
>>>         Ian.
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