diff -r c6cee1d030fc xen/arch/x86/hvm/hvm.c
--- a/xen/arch/x86/hvm/hvm.c	Thu Sep 02 17:42:19 2010 +0200
+++ b/xen/arch/x86/hvm/hvm.c	Mon Sep 06 12:45:56 2010 +0200
@@ -2039,6 +2039,10 @@ int hvm_msr_read_intercept(unsigned int 
 
     switch ( msr )
     {
+    case MSR_EFER:
+        *msr_content = v->arch.hvm_vcpu.guest_efer;
+        break;
+
     case MSR_IA32_TSC:
         *msr_content = hvm_get_guest_tsc(v);
         break;
@@ -2138,6 +2142,11 @@ int hvm_msr_write_intercept(unsigned int
 
     switch ( msr )
     {
+    case MSR_EFER:
+        if ( hvm_set_efer(msr_content) )
+           return X86EMUL_EXCEPTION;
+        break;
+
     case MSR_IA32_TSC:
         hvm_set_guest_tsc(v, msr_content);
         break;
diff -r c6cee1d030fc xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Thu Sep 02 17:42:19 2010 +0200
+++ b/xen/arch/x86/hvm/svm/svm.c	Mon Sep 06 12:45:56 2010 +0200
@@ -116,11 +116,6 @@ long_mode_do_msr_write(unsigned int msr,
 
     switch ( msr )
     {
-    case MSR_EFER:
-        if ( hvm_set_efer(msr_content) )
-            return HNDL_exception_raised;
-        break;
-
     case MSR_IA32_MC4_MISC: /* Threshold register */
     case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
         /*
@@ -1042,10 +1037,6 @@ static int svm_msr_read_intercept(unsign
 
     switch ( msr )
     {
-    case MSR_EFER:
-        *msr_content = v->arch.hvm_vcpu.guest_efer;
-        break;
-
     case MSR_IA32_SYSENTER_CS:
         *msr_content = v->arch.hvm_svm.guest_sysenter_cs;
         break;
diff -r c6cee1d030fc xen/arch/x86/hvm/vmx/vmx.c
--- a/xen/arch/x86/hvm/vmx/vmx.c	Thu Sep 02 17:42:19 2010 +0200
+++ b/xen/arch/x86/hvm/vmx/vmx.c	Mon Sep 06 12:45:56 2010 +0200
@@ -172,10 +172,6 @@ long_mode_do_msr_read(unsigned int msr, 
 
     switch ( msr )
     {
-    case MSR_EFER:
-        *msr_content = v->arch.hvm_vcpu.guest_efer;
-        break;
-
     case MSR_FS_BASE:
         *msr_content = __vmread(GUEST_FS_BASE);
         break;
@@ -224,11 +220,6 @@ long_mode_do_msr_write(unsigned int msr,
 
     switch ( msr )
     {
-    case MSR_EFER:
-        if ( hvm_set_efer(msr_content) )
-            goto exception_raised;
-        break;
-
     case MSR_FS_BASE:
     case MSR_GS_BASE:
     case MSR_SHADOW_GS_BASE:
@@ -270,7 +261,6 @@ long_mode_do_msr_write(unsigned int msr,
  uncanonical_address:
     HVM_DBG_LOG(DBG_LEVEL_0, "Not cano address of msr write %x", msr);
     vmx_inject_hw_exception(TRAP_gp_fault, 0);
- exception_raised:
     return HNDL_exception_raised;
 }
 
@@ -369,18 +359,7 @@ long_mode_do_msr_read(unsigned int msr, 
 static enum handler_return
 long_mode_do_msr_write(unsigned int msr, uint64_t msr_content)
 {
-    switch ( msr )
-    {
-    case MSR_EFER:
-        if ( hvm_set_efer(msr_content) )
-            return HNDL_exception_raised;
-        break;
-
-    default:
-        return HNDL_unhandled;
-    }
-
-    return HNDL_done;
+    return HNDL_unhandled;
 }
 
 #endif /* __i386__ */