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Re: [Xen-devel] [PATCH] x86: propagate pat caching on the shadow l1 (uns

To: Jean Guyader <Jean.Guyader@xxxxxxxxxx>
Subject: Re: [Xen-devel] [PATCH] x86: propagate pat caching on the shadow l1 (unstable)
From: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Date: Mon, 26 Apr 2010 11:35:04 +0100
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At 11:33 +0100 on 26 Apr (1272281626), Jean Guyader wrote:
> On Mon, Apr 26, 2010 at 11:31:42AM +0100, Jean Guyader wrote:
> > (patch against xen-unstable)
> > 
> > PAT caching was only propagated if has_arch_pdevs(), causing the
> > hvm_get_mem_pinned_cacheattr() to be ignored in the non passthrough
> > case.
> > 
> > l1_disallow_mask() needs to be relaxed.
> > 
> > Signed-off-by: Jean Guyader <jean.guyader@xxxxxxxxxx>
> 
> (missing attachement)
> 
> Signed-off-by: Jean Guyader <jean.guyader@xxxxxxxxxx>

Acked-by: Tim Deegan <Tim.Deegan@xxxxxxxxxx>


Content-Description: shadow_caching_closer_unstable.patch
> diff -r f766f2142a85 xen/arch/x86/mm.c
> --- a/xen/arch/x86/mm.c       Mon Apr 26 06:52:44 2010 +0100
> +++ b/xen/arch/x86/mm.c       Mon Apr 26 11:30:27 2010 +0100
> @@ -158,7 +158,8 @@
>      ((d != dom_io) &&                                           \
>       (rangeset_is_empty((d)->iomem_caps) &&                     \
>        rangeset_is_empty((d)->arch.ioport_caps) &&               \
> -      !has_arch_pdevs(d)) ?                                     \
> +      !has_arch_pdevs(d) &&                                     \
> +      !is_hvm_domain(d)) ?                                      \
>       L1_DISALLOW_MASK : (L1_DISALLOW_MASK & ~PAGE_CACHE_ATTRS))
>  
>  #ifdef __x86_64__
> diff -r f766f2142a85 xen/arch/x86/mm/shadow/multi.c
> --- a/xen/arch/x86/mm/shadow/multi.c  Mon Apr 26 06:52:44 2010 +0100
> +++ b/xen/arch/x86/mm/shadow/multi.c  Mon Apr 26 11:30:27 2010 +0100
> @@ -565,7 +565,6 @@
>       * caching attributes in the shadows to match what was asked for.
>       */
>      if ( (level == 1) && is_hvm_domain(d) &&
> -         iomem_access_permitted(d, mfn_x(target_mfn), mfn_x(target_mfn) + 1) 
> &&
>           !is_xen_heap_mfn(mfn_x(target_mfn)) )
>      {
>          unsigned int type;
> @@ -581,20 +580,24 @@
>              sflags |= pat_type_2_pte_flags(type);
>          else if ( d->arch.hvm_domain.is_in_uc_mode )
>              sflags |= pat_type_2_pte_flags(PAT_TYPE_UNCACHABLE);
> -        else if ( p2mt == p2m_mmio_direct )
> -            sflags |= get_pat_flags(v,
> -                                    gflags,
> -                                    gfn_to_paddr(target_gfn),
> -                                    ((paddr_t)mfn_x(target_mfn)) << 
> PAGE_SHIFT,
> -                                    MTRR_TYPE_UNCACHABLE); 
> -        else if ( iommu_snoop )
> -            sflags |= pat_type_2_pte_flags(PAT_TYPE_WRBACK);
> -        else
> -            sflags |= get_pat_flags(v,
> -                                    gflags,
> -                                    gfn_to_paddr(target_gfn),
> -                                    ((paddr_t)mfn_x(target_mfn)) << 
> PAGE_SHIFT,
> -                                    NO_HARDCODE_MEM_TYPE);
> +        else
> +            if ( iomem_access_permitted(d, mfn_x(target_mfn), 
> mfn_x(target_mfn) + 1) )
> +            {
> +                if ( p2mt == p2m_mmio_direct )
> +                    sflags |= get_pat_flags(v,
> +                            gflags,
> +                            gfn_to_paddr(target_gfn),
> +                            ((paddr_t)mfn_x(target_mfn)) << PAGE_SHIFT,
> +                            MTRR_TYPE_UNCACHABLE); 
> +                else if ( iommu_snoop )
> +                    sflags |= pat_type_2_pte_flags(PAT_TYPE_WRBACK);
> +                else
> +                    sflags |= get_pat_flags(v,
> +                            gflags,
> +                            gfn_to_paddr(target_gfn),
> +                            ((paddr_t)mfn_x(target_mfn)) << PAGE_SHIFT,
> +                            NO_HARDCODE_MEM_TYPE);
> +            }
>      }
>  
>      // Set the A&D bits for higher level shadows.


-- 
Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, XenServer Engineering
Citrix Systems UK Ltd.  (Company #02937203, SL9 0BG)

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