At 03:00 +0100 on 18 Jun (1245294045), zhujun wrote:
> Hi, Friends
> I am going over shadow page table code and have a question
> about oos optimization. When shadow page table is established, if a
> guest page table entry marked as Dirty=0, the corresponding shadow
> page table entry clears R/W bit. Thus, when the guest modifies the
> page frame, xen?s page fault handler marks the guest page table?s
> entry as Dirty=1. Also, the guest page table is put into oos list. My
> question is if the guest clears the Dirty bit, how does hypervisor
> know it and when is the Dirty bit set again?
The hypervisor doesn't know it; the dirty bit will be set again the next
time Xen's pagetable walker sees that PTE when it's handling a write
operation.
The shadow PTE will have its R/W bit cleared the next time Xen
propagates the guest PTE to the shadows, which will happen either on a
page fault or when the L1 pagetable is brought back into sync (e.g. by a
guest TLB flush).
> If guest os modifies the page frame again, does the guest page table
> entry?s Dirty bit reflect this information immediately?
No. This is the same behaviour as hardware MMUs, which don't re-set the
dirty bit on a TLB hit. If you want to be sure that your PTE dirty bits
are up to date you have to flush the TLB.
Cheers,
Tim.
--
Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, Citrix Systems (R&D) Ltd.
[Company #02300071, SL9 0DZ, UK.]
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