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Re: [Xen-devel] [PATCH] x86: add SSE-based copy_page()
| To: | Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>, "Cui, Dexuan" <dexuan.cui@xxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxxxx> |
|---|---|
| Subject: | Re: [Xen-devel] [PATCH] x86: add SSE-based copy_page() |
| From: | Keir Fraser <keir.fraser@xxxxxxxxxxxxx> |
| Date: | Tue, 13 Jan 2009 08:13:27 +0000 |
| Cc: | xen-devel@xxxxxxxxxxxxxxxxxxx |
| Delivery-date: | Tue, 13 Jan 2009 00:13:36 -0800 |
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| Thread-topic: | [Xen-devel] [PATCH] x86: add SSE-based copy_page() |
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On 12/01/2009 23:29, "Dan Magenheimer" <dan.magenheimer@xxxxxxxxxx> wrote: > I finally got around to measuring this. On my two machines, > an Intel "Weybridge" box and an Intel TBD quadcore box, > the new sse2 code was at best nearly the same for cold cache > and much worse for warm cache. > > I can't explain the sampling variation as I have interrupts off, > a lock held, and pre-warmed TLB... I suppose maybe another > processor could be causing rare TLB misses? But in any case > the min number is probably best for comparison. > > I'm guessing the gcc optimizer for the memcpy code was tuned > for an Intel pipeline... Jan, were you measuring on an > AMD processor? > > I've included the raw data and measurement code below. Seems like unless we dynamically choose the copy routine, we're better off without the SSE2 alternative. Shall I revert it then? -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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