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Re: [Xen-devel] RE: [patch][vtd] Remove ASSERT in hvmloader.c whenassign
| To: | "Zhang, Li" <li.zhang@xxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [Xen-devel] RE: [patch][vtd] Remove ASSERT in hvmloader.c whenassigning disk controller to a guest |
| From: | Keir Fraser <keir.fraser@xxxxxxxxxxxxx> |
| Date: | Wed, 25 Jun 2008 15:46:53 +0100 |
| Delivery-date: | Wed, 25 Jun 2008 07:47:35 -0700 |
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| Thread-index: | AcjWta1A49gT7Ps4RHaMe8nse4Bn7gAAVCFqAAYNOIAAAHUk0AAAUdjH |
| Thread-topic: | [Xen-devel] RE: [patch][vtd] Remove ASSERT in hvmloader.c whenassigning disk controller to a guest |
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On 25/6/08 15:38, "Zhang, Li" <li.zhang@xxxxxxxxx> wrote: >> If the device is not PIIX3 IDE, we also should do the two > pci_writew(). >> The 0x40 and 0x42 are timing registers of IDE0 and IDE1, and they are >> used to enable the IDE command decoding function. >> And from the PIIX3, ICH to ICH10, the IDE timing registers addresses > are >> the same. So I think removing the ASSERT is OK. The original comment > in >> the file is a little puzzling. So the registers exist in all *Intel* chipsets that we care about. What about other vendors? Should we make the pci_writew() invocations conditional on vendor_id==0x8086? -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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