WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-devel

RE: [Xen-devel] Question about implementation of 32-bit guestson64-bit h

To: "Keir Fraser" <Keir.Fraser@xxxxxxxxxxxx>, "Vessey, Bruce A" <Bruce.Vessey@xxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: RE: [Xen-devel] Question about implementation of 32-bit guestson64-bit hypervisor (IDT-related)
From: "Nakajima, Jun" <jun.nakajima@xxxxxxxxx>
Date: Fri, 7 Dec 2007 21:54:27 -0800
Cc: Ian Pratt <Ian.Pratt@xxxxxxxxxxxxx>, "Guminski, Stephen A" <Stephen.Guminski@xxxxxxxxxx>, Mark Williamson <mark.williamson@xxxxxxxxxxxx>
Delivery-date: Fri, 07 Dec 2007 21:57:41 -0800
Envelope-to: www-data@xxxxxxxxxxxxxxxxxx
In-reply-to: <C37F797B.11169%Keir.Fraser@xxxxxxxxxxxx>
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
References: <C37F745E.1115B%Keir.Fraser@xxxxxxxxxxxx> <C37F797B.11169%Keir.Fraser@xxxxxxxxxxxx>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Thread-index: Acg48YXl4py+oS2vQwSgG5xRZucqnQADRenAAATU4YAAAt1pEgAAww/TAA9i1rA=
Thread-topic: [Xen-devel] Question about implementation of 32-bit guestson64-bit hypervisor (IDT-related)
Keir Fraser wrote:
> On 7/12/07 22:06, "Keir Fraser" <Keir.Fraser@xxxxxxxxxxxx> wrote:
> 
> > Yes. I believe that the Intel manuals are incorrect in stating that
PAE
> > pagetables are restricted to 36-bit addressing. Processors which
support
> > long mode have their physical address size advertised in CPUID, and
I'm
> > pretty sure that addresses up to that size can be poked into 8-byte
> > pagetable entries whether the pagetable format is 64-bit-mode or
pae-mode.
> > AMD state explicitly in their manual that PAE pagetables can address
up to
> > 52 bits, just like 64-bit pagetables, and that this is the
architectural
> > limit. Furthermore, you guys (Unisys) have done testing on big
memory ES7000
> > systems (>128GB), and those are Intel boxes -- and I expect some of
your
> > testing has been 32-bit HVM guests? Given we allocate larger
addresses
> > first, this would confirm that Intel really does allow addresses
>64GB in
> > PAE pagetables in practice.
> 
> Although Intel SDM Vol 3A Section 3.8 makes it look like PAE only
supports
> 36-bit addressing, the manual simply hasn't been updated properly.
There are
> various references elsewhere in Vol 3 that make it clear that PAE
addressing
> is extended on Intel64 processors that have more address lines. The
clearest
> statement I can find is the second footnote of Section 22.3.1.6 in Vol
3B
> (the latest Vol 3B, dated Nov 2007). I'm glad Intel don't hide these
details
> away. ;-)

You should be able to find this in SDM Vol 3A:
3.8.1 Enhanced Legacy PAE Paging
On Intel 64 processors, the page directory pointer entry supports
physical address size of the underlying implementation (reported by
CPUID.80000008H). Legacy PAE enabled paging [see Section 3.8.2, "Linear
Address Translation With PAE Enabled (4-KByte Pages)" and Section 3.8.3,
"Linear Address Translation With PAE Enabled (2-MByte Pages)"] can
address physical memory greater than 64-GByte if the implementation's
physical address size is greater than 36 bits.

> 
>  -- Keir
> 

Jun
---
Intel Open Source Technology Center

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel