Re: [Xen-devel] [PATCH] 3/3: MCA/MCE correctable error handling
On Wednesday 22 August 2007 18:10:24 Keir Fraser wrote:
> On 22/8/07 17:05, "Keir Fraser" <keir@xxxxxxxxxxxxx> wrote:
> >> The polling routine that is in the -unstable tree (the version taken
> >> from Linux) runs every 15 seconds without adjustments.
> >> 1Hz causes too much system load for a healthy system IMO.
> >> That's why I introduced the adjustments with use of hw threshold
> >> registers to come to a compromise solution.
> > What's the deal here? Do correctable errors not cause an MCE, yet are
> > still detected via the machine-check architecture (albeit by a polling
> > method)?
The deal here is, detect correctable errors via polling und uncorrectable
errors via MCE.
This patchset is about correctable errors.
> > Are there going to be patches on the Linux side to pick up this MCA info?
> > What is Linux going to do with it, apart from log it (which Xen can
> > already do itself)? Or is this all Solaris-specific?
The general idea is the Dom0 picks up this MCA info and a) uses
the error-handling infrastructure provided for the non-virtualized form
and b) will use hypercalls to tell xen to also report MCA to a DomU and/or
kill a DomU.
Some hw features for self-healing can only use Dom0 (because registers
sit in the PCI extended config space, Xen doesn't have access to) and some
can use Xen itself.
I wrote a demo driver that mainly tests that the Dom0 actually receives the
MCA info for NetBSD/Xen (Sun prefers to look into BSD licensed code).
It should be easy to port it to Linux.
> Oh, and is AMD-specific code really needed in non-fatal.c? I though the MCA
> stuff was architectural now rather than vendor specific? If there are
> vendor-specific extensions then they belong in the vendor's .c file.
AMD-specific is the use of the hw register code. Intel has some additional
machine check MSR's containing the register set. Intel may add a structure
to patch 2/3 that make use of them. Should I move the amd polling handler to
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