On Sun, Mar 26, 2006 at 11:08:09PM +0200, Muli Ben-Yehuda wrote:
> The following two patches, against the xen-unstable and linux-2.6-xen
> repositories, introduce proof-of-concept IOMMU support in Xen.
Signed-off-by: Muli Ben-Yehuda <mulix@xxxxxxxxx>
Signed-off-by: Jon Mason <jdmason@xxxxxxxxxx>
diff -Naurp -X /home/muli/w/dontdiff vanilla.xenlinux/arch/x86_64/Kconfig
xenlinux/arch/x86_64/Kconfig
--- vanilla.xenlinux/arch/x86_64/Kconfig 2006-03-16 10:01:19.000000000
+0200
+++ xenlinux/arch/x86_64/Kconfig 2006-03-26 17:15:52.000000000 +0200
@@ -121,7 +121,6 @@ endchoice
config X86_64_XEN
bool "Enable Xen compatible kernel"
- select SWIOTLB
help
This option will compile a kernel compatible with Xen hypervisor
@@ -399,6 +398,24 @@ config GART_IOMMU
and a software emulation used on other systems.
If unsure, say Y.
+config CALGARY_IOMMU
+ bool "IBM x366 server IOMMU"
+ default y
+ depends on PCI && EXPERIMENTAL
+ help
+ Support for hardware IOMMUs in IBM's xSeries x366 and x460
+ systems. Needed to run systems with more than 3GB of memory
+ properly with 32-bit PCI devices that do not support DAC
+ (Double Address Cycle). Calgary also supports bus level
+ isolation, where all DMAs pass through the IOMMU. This
+ prevents them from going anywhere except their intended
+ destination. This catches hard-to-find kernel bugs and
+ mis-behaving drivers and devices that do not use the DMA-API
+ properly to set up their DMA buffers. The IOMMU can be
+ turned off at boot time with the iommu=off parameter.
+ Normally the kernel will make the right choice by itself.
+ If unsure, say Y.
+
# need this always enabled with GART_IOMMU for the VIA workaround
config SWIOTLB
bool
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/Makefile
xenlinux/arch/x86_64/kernel/Makefile
--- vanilla.xenlinux/arch/x86_64/kernel/Makefile 2006-03-07
23:11:51.000000000 +0200
+++ xenlinux/arch/x86_64/kernel/Makefile 2006-03-26 17:17:02.000000000
+0200
@@ -31,6 +31,7 @@ obj-$(CONFIG_SOFTWARE_SUSPEND) += suspen
obj-$(CONFIG_CPU_FREQ) += cpufreq/
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_GART_IOMMU) += pci-gart.o aperture.o
+obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary.o tce.o
obj-$(CONFIG_SWIOTLB) += pci-swiotlb.o
obj-$(CONFIG_KPROBES) += kprobes.o
obj-$(CONFIG_X86_PM_TIMER) += pmtimer.o
@@ -55,7 +56,7 @@ dmi_scan-y += ../../i386/kernel/dmi_sc
ifdef CONFIG_XEN
time-y += ../../i386/kernel/time-xen.o
-pci-dma-y += ../../i386/kernel/pci-dma-xen.o
+# pci-dma-y += ../../i386/kernel/pci-dma-xen.o
microcode-$(subst m,y,$(CONFIG_MICROCODE)) :=
../../i386/kernel/microcode-xen.o
quirks-y := ../../i386/kernel/quirks-xen.o
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/pci-calgary.c
xenlinux/arch/x86_64/kernel/pci-calgary.c
--- vanilla.xenlinux/arch/x86_64/kernel/pci-calgary.c 1970-01-01
02:00:00.000000000 +0200
+++ xenlinux/arch/x86_64/kernel/pci-calgary.c 2006-03-26 21:53:05.000000000
+0200
@@ -0,0 +1,970 @@
+/*
+ * Derived from arch/powerpc/kernel/iommu.c
+ *
+ * Copyright (C) 2006 Jon Mason <jdmason@xxxxxxxxxx>, IBM Corporation
+ * Copyright (C) 2006 Muli Ben-Yehuda <mulix@xxxxxxxxx>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/pci_ids.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <asm/proto.h>
+#include <asm/calgary.h>
+#include <asm/tce.h>
+#include <asm/pci-direct.h>
+#include <asm/system.h>
+#include <asm/dma.h>
+
+#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
+#define PCI_VENDOR_DEVICE_ID_CALGARY \
+ (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
+
+/* we need these for register space address calculation */
+#define START_ADDRESS 0xfe000000
+#define CHASSIS_BASE 0
+#define ONE_BASED_CHASSIS_NUM 1
+
+/* register offsets inside the host bridge space */
+#define PHB_PLSSR_OFFSET 0x0120
+#define PHB_CONFIG_RW_OFFSET 0x0160
+#define PHB_IOBASE_BAR_LOW 0x0170
+#define PHB_IOBASE_BAR_HIGH 0x0180
+#define PHB_MEM_1_LOW 0x0190
+#define PHB_MEM_1_HIGH 0x01A0
+#define PHB_IO_ADDR_SIZE 0x01B0
+#define PHB_MEM_1_SIZE 0x01C0
+#define PHB_MEM_ST_OFFSET 0x01D0
+#define PHB_DOSHOLE_OFFSET 0x08E0
+#define PHB_AER_OFFSET 0x0200
+#define PHB_CONFIG_0_HIGH 0x0220
+#define PHB_CONFIG_0_LOW 0x0230
+#define PHB_CONFIG_0_END 0x0240
+#define PHB_MEM_2_LOW 0x02B0
+#define PHB_MEM_2_HIGH 0x02C0
+#define PHB_MEM_2_SIZE_HIGH 0x02D0
+#define PHB_MEM_2_SIZE_LOW 0x02E0
+
+/* PHB_CONFIG_RW */
+#define PHB_TCE_ENABLE 0x20000000
+#define PHB_DAC_DISABLE 0x01000000
+#define PHB_MEM2_ENABLE 0x00400000
+/* TAR (Table Address Register) */
+#define TAR_SW_BITS 0x0000ffffffff800fUL
+#define TAR_VALID 0x0000000000000008UL
+
+#define MAX_NUM_NODES 1 /* max number of NUMA nodes */
+#define MAX_NUM_OF_PHBS 2 /* how many PHBs in total? */
+#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * 2) /* max
dev->bus->number */
+#define PHBS_PER_CALGARY 4
+
+/* register offsets in Calgary's internal register space */
+static const unsigned long tar_offsets[] = {
+ 0x0580 /* TAR0 */,
+ 0x0588 /* TAR1 */,
+ 0x0590 /* TAR2 */,
+ 0x0598 /* TAR3 */
+};
+
+static const unsigned long split_queue_offsets[] = {
+ 0x4870 /* SPLIT QUEUE 0 */,
+ 0x5870 /* SPLIT QUEUE 1 */,
+ 0x6870 /* SPLIT QUEUE 2 */,
+ 0x7870 /* SPLIT QUEUE 3 */
+};
+
+static const unsigned long phb_offsets[] = {
+ 0x8000 /* PHB0 */,
+ 0x9000 /* PHB1 */,
+ 0xA000 /* PHB2 */,
+ 0xB000 /* PHB3 */
+};
+
+void* tce_table_kva[MAX_NUM_OF_PHBS * MAX_NUM_NODES];
+unsigned int specified_table_size = TCE_TABLE_SIZE_256K;
+static int translate_empty_slots __read_mostly = 0;
+static int calgary_detected __read_mostly = 0;
+
+/*
+ * some X servers do DMA directly from userspace, without a proper mapping :-(
+ * enable this to give PHB 0 (where the on board graphics adapter lives) a
+ * static identity mapping, disable this to get full isolation for PHB 0.
+ */
+static int translate_phb0 __read_mostly = 1;
+
+static void tce_cache_blast(struct iommu_table *tbl);
+
+/* enable this to stress test the chip's TCE cache */
+#ifdef CONFIG_IOMMU_DEBUG
+static inline void tce_cache_blast_stress(struct iommu_table *tbl)
+{
+ tce_cache_blast(tbl);
+}
+#else
+static inline void tce_cache_blast_stress(struct iommu_table *tbl)
+{
+}
+#endif /* BLAST_TCE_CACHE_ON_UNMAP */
+
+static inline unsigned int num_dma_pages(unsigned long dma, unsigned int
dmalen)
+{
+ unsigned int npages;
+
+ npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
+ npages >>= PAGE_SHIFT;
+
+ return npages;
+}
+
+static inline int translate_phb(struct pci_dev* dev)
+{
+ /* not phb0? translate */
+ if (dev->bus->number != 0)
+ return 1;
+
+ if (translate_phb0)
+ return 1;
+
+ return 0;
+}
+
+static void iommu_range_reserve(struct iommu_table *tbl,
+ unsigned long start_addr, unsigned int npages)
+{
+ unsigned long index;
+ unsigned long end;
+
+ index = start_addr >> PAGE_SHIFT;
+
+ /* bail out if we're asked to reserve a region we don't cover */
+ if (index >= tbl->it_size)
+ return;
+
+ end = index + npages;
+ if (end > tbl->it_size) /* don't go off the table */
+ end = tbl->it_size;
+
+ while (index < end) {
+ if (test_bit(index, tbl->it_map))
+ printk(KERN_ERR "Calgary: entry already allocated at "
+ "0x%lx tbl %p dma 0x%lx npages %u\n",
+ index, tbl, start_addr, npages);
+ ++index;
+ }
+ set_bit_string(tbl->it_map, start_addr >> PAGE_SHIFT, npages);
+}
+
+static unsigned long iommu_range_alloc(struct iommu_table *tbl,
+ unsigned int npages)
+{
+ unsigned long offset;
+
+ BUG_ON(npages == 0);
+
+ offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
+ tbl->it_size, npages);
+ if (offset == ~0UL) {
+ tce_cache_blast(tbl);
+ offset = find_next_zero_string(tbl->it_map, 0,
+ tbl->it_size, npages);
+ if (offset == ~0UL) {
+ printk(KERN_WARNING "Calgary: IOMMU full.\n");
+ if (panic_on_overflow)
+ panic("Calgary: fix the allocator.\n");
+ else
+ return bad_dma_address;
+ }
+ }
+
+ set_bit_string(tbl->it_map, offset, npages);
+ tbl->it_hint = offset + npages;
+ BUG_ON(tbl->it_hint > tbl->it_size);
+
+ return offset;
+}
+
+static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
+ unsigned int npages, int direction)
+{
+ unsigned long entry, flags;
+ dma_addr_t ret = bad_dma_address;
+
+ spin_lock_irqsave(&tbl->it_lock, flags);
+
+ entry = iommu_range_alloc(tbl, npages);
+
+ if (unlikely(entry == bad_dma_address))
+ goto error;
+
+ /* set the return dma address */
+ ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
+
+ /* put the TCEs in the HW table */
+ tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
+ direction);
+
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+
+ return ret;
+
+error:
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+ printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
+ "iommu %p\n", npages, tbl);
+ return bad_dma_address;
+}
+
+static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
+ unsigned int npages)
+{
+ unsigned long entry;
+ unsigned long i;
+
+ entry = dma_addr >> PAGE_SHIFT;
+
+ BUG_ON(entry + npages > tbl->it_size);
+
+ tce_free(tbl, entry, npages);
+
+ for (i = 0; i < npages; ++i) {
+ if (!test_bit(entry + i, tbl->it_map))
+ printk(KERN_ERR "Calgary: bit is off at 0x%lx "
+ "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
+ entry + i, tbl, dma_addr, entry, npages);
+ }
+
+ __clear_bit_string(tbl->it_map, entry, npages);
+
+ tce_cache_blast_stress(tbl);
+}
+
+static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
+ unsigned int npages)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&tbl->it_lock, flags);
+
+ __iommu_free(tbl, dma_addr, npages);
+
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+}
+
+static void __calgary_unmap_sg(struct iommu_table *tbl,
+ struct scatterlist *sglist, int nelems, int direction)
+{
+ while (nelems--) {
+ unsigned int npages;
+ dma_addr_t dma = sglist->dma_address;
+ unsigned int dmalen = sglist->dma_length;
+
+ if (dmalen == 0)
+ break;
+
+ npages = num_dma_pages(dma, dmalen);
+ __iommu_free(tbl, dma, npages);
+ sglist++;
+ }
+}
+
+void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
+ int nelems, int direction)
+{
+ unsigned long flags;
+ struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
+
+ if (!translate_phb(to_pci_dev(dev)))
+ return;
+
+ spin_lock_irqsave(&tbl->it_lock, flags);
+
+ __calgary_unmap_sg(tbl, sglist, nelems, direction);
+
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+}
+
+static int calgary_nontranslate_map_sg(struct device* dev,
+ struct scatterlist *sg, int nelems, int direction)
+{
+ int i;
+
+ for (i = 0; i < nelems; i++ ) {
+ struct scatterlist *s = &sg[i];
+ BUG_ON(!s->page);
+ s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
+ s->dma_length = s->length;
+ }
+ return nelems;
+}
+
+int calgary_map_sg(struct device *dev, struct scatterlist *sg,
+ int nelems, int direction)
+{
+ struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
+ unsigned long flags;
+ unsigned long vaddr;
+ unsigned int npages;
+ unsigned long entry;
+ int i;
+
+ if (!translate_phb(to_pci_dev(dev)))
+ return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
+
+ spin_lock_irqsave(&tbl->it_lock, flags);
+
+ for (i = 0; i < nelems; i++ ) {
+ struct scatterlist *s = &sg[i];
+ BUG_ON(!s->page);
+
+ vaddr = (unsigned long)page_address(s->page) + s->offset;
+ npages = num_dma_pages(vaddr, s->length);
+
+ entry = iommu_range_alloc(tbl, npages);
+ if (entry == bad_dma_address) {
+ /* makes sure unmap knows to stop */
+ s->dma_length = 0;
+ goto error;
+ }
+
+ s->dma_address = (entry << PAGE_SHIFT) | s->offset;
+
+ /* insert into HW table */
+ tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
+ direction);
+
+ s->dma_length = s->length;
+ }
+
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+
+ return nelems;
+error:
+ __calgary_unmap_sg(tbl, sg, nelems, direction);
+ for (i = 0; i < nelems; i++) {
+ sg[i].dma_address = bad_dma_address;
+ sg[i].dma_length = 0;
+ }
+ spin_unlock_irqrestore(&tbl->it_lock, flags);
+ return 0;
+}
+
+dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
+ size_t size, int direction)
+{
+ dma_addr_t dma_handle = bad_dma_address;
+ unsigned long uaddr;
+ unsigned int npages;
+ struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
+
+ uaddr = (unsigned long)vaddr;
+ npages = num_dma_pages(uaddr, size);
+
+ if (translate_phb(to_pci_dev(dev)))
+ dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
+ else
+ dma_handle = virt_to_bus(vaddr);
+
+ return dma_handle;
+}
+
+void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
+ unsigned int npages;
+
+ if (!translate_phb(to_pci_dev(dev)))
+ return;
+
+ npages = num_dma_pages(dma_handle, size);
+ iommu_free(tbl, dma_handle, npages);
+}
+
+void* calgary_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag)
+{
+ void *ret = NULL;
+ dma_addr_t mapping;
+ unsigned int npages, order;
+ struct iommu_table *tbl;
+
+ tbl = to_pci_dev(dev)->bus->self->sysdata;
+
+ size = PAGE_ALIGN(size); /* size rounded up to full pages */
+ npages = size >> PAGE_SHIFT;
+ order = get_order(size);
+
+ /* alloc enough pages (and possibly more) */
+ ret = (void *)__get_free_pages(flag, order);
+ if (!ret)
+ goto error;
+ memset(ret, 0, size);
+
+ if (translate_phb(to_pci_dev(dev))) {
+ /* set up tces to cover the allocated range */
+ mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
+ if (mapping == bad_dma_address)
+ goto free;
+
+ *dma_handle = mapping;
+ } else /* non translated slot */
+ *dma_handle = virt_to_bus(ret);
+
+ return ret;
+
+free:
+ free_pages((unsigned long)ret, get_order(size));
+ ret = NULL;
+error:
+ return ret;
+}
+
+static struct dma_mapping_ops calgary_dma_ops = {
+ .alloc_coherent = calgary_alloc_coherent,
+ .map_single = calgary_map_single,
+ .unmap_single = calgary_unmap_single,
+ .map_sg = calgary_map_sg,
+ .unmap_sg = calgary_unmap_sg,
+};
+
+static inline int busno_to_phbid(unsigned char num)
+{
+ return bus_to_phb(num) % PHBS_PER_CALGARY;
+}
+
+static inline unsigned long split_queue_offset(unsigned char num)
+{
+ size_t idx = busno_to_phbid(num);
+
+ return split_queue_offsets[idx];
+}
+
+static inline unsigned long tar_offset(unsigned char num)
+{
+ size_t idx = busno_to_phbid(num);
+
+ return tar_offsets[idx];
+}
+
+static inline unsigned long phb_offset(unsigned char num)
+{
+ size_t idx = busno_to_phbid(num);
+
+ return phb_offsets[idx];
+}
+
+static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long
offset)
+{
+ unsigned long target = ((unsigned long)bar) | offset;
+ return (void __iomem*)target;
+}
+
+static void tce_cache_blast(struct iommu_table *tbl)
+{
+ u64 val;
+ u32 aer;
+ int i = 0;
+ void __iomem *bbar = tbl->bbar;
+ void __iomem *target;
+
+ /* disable arbitration on the bus */
+ target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
+ aer = readl(target);
+ writel(0, target);
+
+ /* read plssr to ensure it got there */
+ target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
PHB_PLSSR_OFFSET);
+ val = readl(target);
+
+ /* poll split queues until all DMA activity is done */
+ target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
+ do {
+ val = readq(target);
+ i++;
+ } while ((val & 0xff) != 0xff && i < 100);
+ if (i == 100)
+ printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
+ "continuing anyway\n");
+
+ /* invalidate TCE cache */
+ target = calgary_reg(bbar, tar_offset(tbl->it_busno));
+ writeq(tbl->tar_val, target);
+
+ /* enable arbitration */
+ target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
+ writel(aer, target);
+ (void)readl(target); /* flush */
+}
+
+static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
+ u64 limit)
+{
+ unsigned int numpages;
+
+ limit = limit | 0xfffff;
+ limit++;
+
+ numpages = ((limit - start) >> PAGE_SHIFT);
+ iommu_range_reserve(dev->sysdata, start, numpages);
+}
+
+static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
+{
+ void __iomem *target;
+ u64 low, high, sizelow;
+ u64 start, limit;
+ struct iommu_table *tbl = dev->sysdata;
+ unsigned char busnum = dev->bus->number;
+ void __iomem *bbar = tbl->bbar;
+
+ /* peripheral MEM_1 region */
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
+ low = be32_to_cpu(readl(target));
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
+ high = be32_to_cpu(readl(target));
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
+ sizelow = be32_to_cpu(readl(target));
+
+ start = (high << 32) | low;
+ limit = sizelow;
+
+ calgary_reserve_mem_region(dev, start, limit);
+}
+
+static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
+{
+ void __iomem *target;
+ u32 val32;
+ u64 low, high, sizelow, sizehigh;
+ u64 start, limit;
+ struct iommu_table *tbl = dev->sysdata;
+ unsigned char busnum = dev->bus->number;
+ void __iomem *bbar = tbl->bbar;
+
+ /* is it enabled? */
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
+ val32 = be32_to_cpu(readl(target));
+ if (!(val32 & PHB_MEM2_ENABLE))
+ return;
+
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
+ low = be32_to_cpu(readl(target));
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
+ high = be32_to_cpu(readl(target));
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
+ sizelow = be32_to_cpu(readl(target));
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
+ sizehigh = be32_to_cpu(readl(target));
+
+ start = (high << 32) | low;
+ limit = (sizehigh << 32) | sizelow;
+
+ calgary_reserve_mem_region(dev, start, limit);
+}
+
+/*
+ * some regions of the IO address space do not get translated, so we
+ * must not give devices IO addresses in those regions. The regions
+ * are the 640KB-1MB region and the two PCI peripheral memory holes.
+ * Reserve all of them in the IOMMU bitmap to avoid giving them out
+ * later.
+ */
+static void __init calgary_reserve_regions(struct pci_dev *dev)
+{
+ unsigned int npages;
+ void __iomem *bbar;
+ unsigned char busnum;
+ u64 start;
+ struct iommu_table *tbl = dev->sysdata;
+
+ bbar = tbl->bbar;
+ busnum = dev->bus->number;
+
+ /* reserve bad_dma_address in case it's a legal address */
+ iommu_range_reserve(tbl, bad_dma_address, 1);
+
+ /* avoid the BIOS/VGA first 640KB-1MB region */
+ start = (640 * 1024);
+ npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
+ iommu_range_reserve(tbl, start, npages);
+
+ /* reserve the two PCI peripheral memory regions in IO space */
+ calgary_reserve_peripheral_mem_1(dev);
+ calgary_reserve_peripheral_mem_2(dev);
+}
+
+static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
+{
+ u64 val64;
+ u64 table_phys;
+ void __iomem *target;
+ int ret;
+ unsigned long rootmfn;
+ struct iommu_table* tbl;
+
+ ret = alloc_tce_table(dev->bus->number, &rootmfn);
+ if (ret)
+ goto done;
+
+ /* Build TCE tables for each PHB */
+ ret = build_tce_table(dev, bbar, rootmfn);
+ if (ret)
+ goto free_table;
+
+ calgary_reserve_regions(dev);
+
+ /* set TARs for each PHB */
+ target = calgary_reg(bbar, tar_offset(dev->bus->number));
+ val64 = be64_to_cpu(readq(target));
+
+ /* zero out all TAR bits under sw control */
+ val64 &= ~TAR_SW_BITS;
+
+ tbl = dev->sysdata;
+ table_phys = (u64)tbl->it_base << PAGE_SHIFT;
+ val64 |= table_phys;
+
+ BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
+ val64 |= (u64) specified_table_size;
+
+ tbl->tar_val = cpu_to_be64(val64);
+ writeq(tbl->tar_val, target);
+ readq(target); /* flush */
+
+ return 0;
+
+free_table:
+ /* FIXME */
+done:
+ return ret;
+}
+
+static void __init calgary_free_tar(struct pci_dev *dev)
+{
+ u64 val64;
+ struct iommu_table *tbl = dev->sysdata;
+ void __iomem *target;
+
+ target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
+ val64 = be64_to_cpu(readq(target));
+ val64 &= ~TAR_SW_BITS;
+ writeq(cpu_to_be64(val64), target);
+ readq(target); /* flush */
+
+ kfree(tbl);
+ dev->sysdata = NULL;
+}
+
+static void __init calgary_enable_translation(struct pci_dev *dev)
+{
+ u32 val32;
+ unsigned char busnum;
+ void __iomem *target;
+ void __iomem *bbar;
+ struct iommu_table *tbl;
+
+ busnum = dev->bus->number;
+ tbl = dev->sysdata;
+ bbar = tbl->bbar;
+
+ /* enable TCE in PHB Config Register */
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
+ val32 = be32_to_cpu(readl(target));
+ val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE;
+
+ printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
+ printk(KERN_INFO "Calgary: misbehaving devices on this bridge will
now\n"
+ "be caught if they try to DMA where they shouldn't.\n");
+
+ writel(cpu_to_be32(val32), target);
+ readl(target); /* flush */
+}
+
+static void __init calgary_disable_translation(struct pci_dev *dev)
+{
+ u32 val32;
+ unsigned char busnum;
+ void __iomem *target;
+ void __iomem *bbar;
+ struct iommu_table *tbl;
+
+ busnum = dev->bus->number;
+ tbl = dev->sysdata;
+ bbar = tbl->bbar;
+
+ /* disable TCE in PHB Config Register */
+ target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
+ val32 = be32_to_cpu(readl(target));
+ val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE);
+
+ printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
+ writel(cpu_to_be32(val32), target);
+ readl(target); /* flush */
+}
+
+static inline unsigned int __init locate_register_space(struct pci_dev *dev)
+{
+ int rionodeid;
+ u32 address;
+
+ rionodeid = (dev->bus->number % 15 > 4) ? 3 : 2;
+ /*
+ * register space address calculation as follows:
+ * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
+ * ChassisBase is always zero for x366/x260/x460
+ * RioNodeId is 2 for first Calgary, 3 for second Calgary
+ */
+ address = START_ADDRESS -
+ (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 15)) +
+ (0x100000) * (rionodeid - CHASSIS_BASE);
+ return address;
+}
+
+static int __init calgary_init_one_nontraslated(struct pci_dev *dev)
+{
+ dev->sysdata = NULL;
+ dev->bus->self = dev;
+
+ return 0;
+}
+
+static int __init calgary_init_one(struct pci_dev *dev)
+{
+ u32 address;
+ void __iomem *bbar;
+ int ret;
+
+ address = locate_register_space(dev);
+ /* map entire 1MB of Calgary config space */
+ bbar = ioremap_nocache(address, 1024 * 1024);
+ if (!bbar) {
+ ret = -ENODATA;
+ goto done;
+ }
+
+ ret = calgary_setup_tar(dev, bbar);
+ if (ret)
+ goto iounmap;
+
+ dev->bus->self = dev;
+ calgary_enable_translation(dev);
+
+ return 0;
+
+iounmap:
+ iounmap(bbar);
+done:
+ return ret;
+}
+
+static int __init calgary_init(void)
+{
+ int i, ret = -ENODEV;
+ struct pci_dev *dev = NULL;
+
+ for (i = 0; i < MAX_NUM_OF_PHBS * MAX_NUM_NODES; i++) {
+ dev = pci_get_device(PCI_VENDOR_ID_IBM,
PCI_DEVICE_ID_IBM_CALGARY, dev);
+ if (!dev)
+ break;
+ if (!translate_phb(dev)) {
+ calgary_init_one_nontraslated(dev);
+ continue;
+ }
+#if 0
+ if (!tce_table_kva[i] && !translate_empty_slots) {
+ pci_dev_put(dev);
+ continue;
+ }
+#endif
+ ret = calgary_init_one(dev);
+ if (ret)
+ goto error;
+ }
+
+ return ret;
+
+error:
+ for (i--; i >= 0; i--) {
+ dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
+ PCI_DEVICE_ID_IBM_CALGARY,
+ dev);
+ if (!translate_phb(dev)) {
+ pci_dev_put(dev);
+ continue;
+ }
+ if (!tce_table_kva[i] && !translate_empty_slots)
+ continue;
+ calgary_disable_translation(dev);
+ calgary_free_tar(dev);
+ pci_dev_put(dev);
+ }
+
+ return ret;
+}
+
+static inline int __init determine_tce_table_size(u64 ram)
+{
+ int ret;
+
+ if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
+ return specified_table_size;
+
+ /*
+ * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
+ * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
+ * larger table size has twice as many entries, so shift the
+ * max ram address by 13 to divide by 8K and then look at the
+ * order of the result to choose between 0-7.
+ */
+ ret = get_order(ram >> 13);
+ if (ret > TCE_TABLE_SIZE_8M)
+ ret = TCE_TABLE_SIZE_8M;
+
+ return ret;
+}
+
+void __init detect_calgary(void)
+{
+ /*
+ * if the user specified iommu=off or iommu=soft or we found
+ * another HW IOMMU already, bail out.
+ */
+ if (swiotlb || no_iommu || iommu_detected)
+ return;
+
+ printk(KERN_INFO "PCI-DMA: detecting Calgary chipset...\n");
+ calgary_detected = 1;
+ printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. "
+ "TCE table spec is %d.\n", specified_table_size);
+
+#if 0
+ specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
+
+ for (bus = 0, calgary = 0;
+ bus < MAX_NUM_OF_PHBS * num_online_nodes() * 2;
+ bus++) {
+ BUG_ON(bus >= MAX_PHB_BUS_NUM * MAX_NUM_NODES);
+ if (read_pci_config(bus, 0, 0, 0) !=
PCI_VENDOR_DEVICE_ID_CALGARY)
+ continue;
+ if ((bus == 0) && !translate_phb0) {
+ /* skip phb0, don't allocate a tbl for it */
+ tce_table_kva[calgary] = NULL;
+ calgary++;
+ continue;
+ }
+ /*
+ * scan the first slot of the PCI bus to see if there
+ * are any devices present
+ */
+ val = read_pci_config(bus, 1, 0, 0);
+ if (val != 0xffffffff || translate_empty_slots) {
+ tbl = alloc_tce_table();
+ if (!tbl)
+ goto cleanup;
+ } else
+ tbl = NULL;
+
+ tce_table_kva[calgary] = tbl;
+ calgary++;
+ }
+
+ if (calgary) {
+ iommu_detected = 1;
+ calgary_detected = 1;
+ printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected. "
+ "TCE table spec is %d.\n", specified_table_size);
+ }
+ return;
+
+cleanup:
+ for (--calgary; calgary >= 0; --calgary)
+ free_tce_table(tce_table_kva[calgary]);
+#endif
+}
+
+int __init calgary_iommu_init(void)
+{
+ int ret;
+
+ if (no_iommu || swiotlb)
+ return -1;
+
+ /* did we detect a differet HW IOMMU? */
+ if (iommu_detected && !calgary_detected)
+ return -1;
+
+ /* ok, we're trying to use Calgary - let's roll */
+ printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
+
+ ret = calgary_init();
+ if (ret) {
+ printk(KERN_ERR "PCI-DMA: Calgary init failed %x, "
+ "falling back to no_iommu\n", ret);
+ if (end_pfn > MAX_DMA32_PFN)
+ printk(KERN_ERR "WARNING more than 4GB of memory, "
+ "32bit PCI may malfunction.\n");
+ return ret;
+ }
+
+ force_iommu = 1;
+ dma_ops = &calgary_dma_ops;
+
+ return 0;
+}
+
+void __init calgary_parse_options(char *p)
+{
+ while (*p) {
+ if (!strncmp(p, "64k", 3))
+ specified_table_size = TCE_TABLE_SIZE_64K;
+ else if (!strncmp(p, "128k", 4))
+ specified_table_size = TCE_TABLE_SIZE_128K;
+ else if (!strncmp(p, "256k", 4))
+ specified_table_size = TCE_TABLE_SIZE_256K;
+ else if (!strncmp(p, "512k", 4))
+ specified_table_size = TCE_TABLE_SIZE_512K;
+ else if (!strncmp(p, "1M", 2))
+ specified_table_size = TCE_TABLE_SIZE_1M;
+ else if (!strncmp(p, "2M", 2))
+ specified_table_size = TCE_TABLE_SIZE_2M;
+ else if (!strncmp(p, "4M", 2))
+ specified_table_size = TCE_TABLE_SIZE_4M;
+ else if (!strncmp(p, "8M", 2))
+ specified_table_size = TCE_TABLE_SIZE_8M;
+
+ if (!strncmp(p, "translate_empty_slots",
+ strlen("translate_empty_slots")))
+ translate_empty_slots = 1;
+
+ if (!strncmp(p, "translate_phb0", strlen("translate_phb0")))
+ translate_phb0 = 1;
+
+ p += strcspn(p, ",");
+ if (*p == ',')
+ ++p;
+ }
+}
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/pci-dma.c
xenlinux/arch/x86_64/kernel/pci-dma.c
--- vanilla.xenlinux/arch/x86_64/kernel/pci-dma.c 2006-03-07
23:11:52.000000000 +0200
+++ xenlinux/arch/x86_64/kernel/pci-dma.c 2006-03-26 17:17:56.000000000
+0200
@@ -7,8 +7,10 @@
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/module.h>
+#include <linux/config.h>
#include <asm/io.h>
#include <asm/proto.h>
+#include <asm/calgary.h>
int iommu_merge __read_mostly = 0;
EXPORT_SYMBOL(iommu_merge);
@@ -33,6 +35,9 @@ int panic_on_overflow __read_mostly = 0;
int force_iommu __read_mostly= 0;
#endif
+/* Set this to 1 if there is a HW IOMMU in the system */
+int iommu_detected __read_mostly = 0;
+
/* Dummy device used for NULL arguments (normally ISA). Better would
be probably a smaller DMA mask, but this is bug-to-bug compatible
to i386. */
@@ -157,6 +162,15 @@ void dma_free_coherent(struct device *de
}
EXPORT_SYMBOL(dma_free_coherent);
+int dma_set_mask(struct device *dev, u64 mask)
+{
+ if (!dev->dma_mask || !dma_supported(dev, mask))
+ return -EIO;
+ *dev->dma_mask = mask;
+ return 0;
+}
+EXPORT_SYMBOL(dma_set_mask);
+
int dma_supported(struct device *dev, u64 mask)
{
if (dma_ops->dma_supported)
@@ -189,15 +203,6 @@ int dma_supported(struct device *dev, u6
}
EXPORT_SYMBOL(dma_supported);
-int dma_set_mask(struct device *dev, u64 mask)
-{
- if (!dev->dma_mask || !dma_supported(dev, mask))
- return -EIO;
- *dev->dma_mask = mask;
- return 0;
-}
-EXPORT_SYMBOL(dma_set_mask);
-
/*
iommu=[size][,noagp][,off][,force][,noforce][,leak][,memaper[=order]][,merge]
[,forcesac][,fullflush][,nomerge][,biomerge]
size set size of iommu (in bytes)
@@ -267,3 +272,21 @@ __init int iommu_setup(char *p)
}
return 1;
}
+
+static int __init pci_iommu_init(void)
+{
+ int rc = 0;
+
+#ifdef CONFIG_CALGARY_IOMMU
+ rc = calgary_iommu_init();
+ if (!rc) /* success? */
+ return 0;
+#endif
+#ifdef CONFIG_GART_IOMMU
+ rc = gart_iommu_init();
+#endif
+ return rc;
+}
+
+/* Must execute after PCI subsystem */
+fs_initcall(pci_iommu_init);
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/pci-gart.c
xenlinux/arch/x86_64/kernel/pci-gart.c
--- vanilla.xenlinux/arch/x86_64/kernel/pci-gart.c 2006-03-07
23:11:52.000000000 +0200
+++ xenlinux/arch/x86_64/kernel/pci-gart.c 2006-03-26 17:18:33.000000000
+0200
@@ -605,7 +605,7 @@ static struct dma_mapping_ops gart_dma_o
.unmap_sg = gart_unmap_sg,
};
-static int __init pci_iommu_init(void)
+int __init gart_iommu_init(void)
{
struct agp_kern_info info;
unsigned long aper_size;
@@ -627,6 +627,10 @@ static int __init pci_iommu_init(void)
if (swiotlb)
return -1;
+ /* Did we detect a different HW IOMMU? */
+ if (iommu_detected && !iommu_aperture)
+ return -1;
+
if (no_iommu ||
(!force_iommu && end_pfn <= MAX_DMA32_PFN) ||
!iommu_aperture ||
@@ -721,10 +725,7 @@ static int __init pci_iommu_init(void)
return 0;
}
-/* Must execute after PCI subsystem */
-fs_initcall(pci_iommu_init);
-
-void gart_parse_options(char *p)
+void __init gart_parse_options(char *p)
{
int arg;
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/setup.c xenlinux/arch/x86_64/kernel/setup.c
--- vanilla.xenlinux/arch/x86_64/kernel/setup.c 2006-03-07 23:11:52.000000000
+0200
+++ xenlinux/arch/x86_64/kernel/setup.c 2006-03-26 17:20:28.000000000 +0200
@@ -67,6 +67,7 @@
#include <asm/swiotlb.h>
#include <asm/sections.h>
#include <asm/gart-mapping.h>
+#include <asm/calgary.h>
/*
* Machine setup..
@@ -388,6 +389,12 @@ static __init void parse_cmdline_early (
iommu_setup(from+6);
}
+#ifdef CONFIG_CALGARY_IOMMU
+ if (!memcmp(from,"calgary=",8)) {
+ calgary_parse_options(from+8);
+ }
+#endif
+
if (!memcmp(from,"oops=panic", 10))
panic_on_oops = 1;
@@ -747,6 +754,9 @@ void __init setup_arch(char **cmdline_p)
#ifdef CONFIG_GART_IOMMU
iommu_hole_init();
#endif
+#ifdef CONFIG_CALGARY_IOMMU
+ detect_calgary();
+#endif
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/arch/x86_64/kernel/setup-xen.c
xenlinux/arch/x86_64/kernel/setup-xen.c
--- vanilla.xenlinux/arch/x86_64/kernel/setup-xen.c 2006-03-24
17:17:04.000000000 +0200
+++ xenlinux/arch/x86_64/kernel/setup-xen.c 2006-03-24 17:18:35.000000000
+0200
@@ -67,6 +67,7 @@
#include <asm/swiotlb.h>
#include <asm/sections.h>
#include <asm/gart-mapping.h>
+#include <asm/calgary.h>
#ifdef CONFIG_XEN
#include <linux/percpu.h>
#include <xen/interface/physdev.h>
diff -Naurp -X /home/muli/w/dontdiff vanilla.xenlinux/arch/x86_64/kernel/tce.c
xenlinux/arch/x86_64/kernel/tce.c
--- vanilla.xenlinux/arch/x86_64/kernel/tce.c 1970-01-01 02:00:00.000000000
+0200
+++ xenlinux/arch/x86_64/kernel/tce.c 2006-03-26 21:56:00.000000000 +0200
@@ -0,0 +1,194 @@
+/*
+ * Derived from arch/powerpc/platforms/pseries/iommu.c
+ *
+ * Copyright (C) 2006 Jon Mason <jdmason@xxxxxxxxxx>, IBM Corporation
+ * Copyright (C) 2006 Muli Ben-Yehuda <mulix@xxxxxxxxx>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/bootmem.h>
+#include <asm/tce.h>
+#include <asm/calgary.h>
+#include <asm/proto.h>
+#include <xen/interface/dom0_ops.h>
+
+void tce_build(struct iommu_table *tbl, unsigned long index,
+ unsigned int npages, unsigned long uaddr, int direction)
+{
+ unsigned long mfn;
+ u64 ioaddr;
+ u64 retaddr;
+ unsigned int access;
+ unsigned int bus;
+
+ bus = tbl->it_busno;
+
+ /* FIXME: sooner or later Xen dies if we give out RO mappings */
+ access = 0x3;
+
+ ioaddr = index << PAGE_SHIFT;
+
+ while (npages--) {
+ mfn = virt_to_mfn(uaddr);
+
+ /* TODO: we should use multicalls here */
+ retaddr = HYPERVISOR_iommu_map(ioaddr, mfn, access, bus,
+ PAGE_SIZE);
+ BUG_ON(retaddr != ioaddr);
+
+ uaddr += PAGE_SIZE;
+ ioaddr += PAGE_SIZE;
+ }
+}
+
+void tce_free(struct iommu_table *tbl, long index, unsigned int npages)
+{
+ u64 ioaddr;
+ int ret;
+
+ ioaddr = index << PAGE_SHIFT;
+
+ while (npages--) {
+ /* TODO: we should use multicalls here */
+ ret = HYPERVISOR_iommu_unmap(ioaddr, tbl->it_busno, PAGE_SIZE);
+ BUG_ON(ret);
+
+ ioaddr += PAGE_SIZE;
+ }
+}
+
+static inline unsigned int table_size_to_number_of_entries(unsigned char size)
+{
+ /*
+ * size is the order of the table, 0-7
+ * smallest table is 8K entries, so shift result by 13 to
+ * multiply by 8K
+ */
+ return (1 << size) << 13;
+}
+
+static int tce_table_setparms(struct pci_dev *dev, struct iommu_table *tbl,
+ unsigned long rootmfn)
+{
+ unsigned int bitmapsz;
+ unsigned long bmppages;
+ int ret;
+
+ tbl->it_busno = dev->bus->number;
+
+ /* set the tce table size - measured in entries */
+ tbl->it_size = table_size_to_number_of_entries(specified_table_size);
+ tbl->it_base = rootmfn;
+
+ /* number of bytes needed for the bitmap */
+ /* size in number of entries; we need one bit per entry */
+ bitmapsz = tbl->it_size / BITS_PER_BYTE;
+ bmppages = __get_free_pages(GFP_KERNEL, get_order(bitmapsz));
+ if (!bmppages) {
+ printk(KERN_ERR "Calgary: cannot allocate bitmap\n");
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ tbl->it_map = (unsigned long*)bmppages;
+
+ memset(tbl->it_map, 0, bitmapsz);
+
+ tbl->it_hint = 0;
+
+ spin_lock_init(&tbl->it_lock);
+
+ return 0;
+
+done:
+ return ret;
+}
+
+int build_tce_table(struct pci_dev *dev, void __iomem* bbar,
+ unsigned long rootmfn)
+{
+ struct iommu_table *tbl;
+ int ret;
+
+ if (dev->sysdata) {
+ printk(KERN_ERR "Calgary: dev %p has sysdata %p\n",
+ dev, dev->sysdata);
+ BUG();
+ }
+
+ tbl = kzalloc(sizeof(struct iommu_table), GFP_KERNEL);
+ if (!tbl) {
+ printk(KERN_ERR "Calgary: error allocating iommu_table\n");
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ ret = tce_table_setparms(dev, tbl, rootmfn);
+ if (ret)
+ goto free_tbl;
+
+ tce_free(tbl, 0, tbl->it_size);
+
+ tbl->bbar = bbar;
+
+ /*
+ * NUMA is already using the bus's sysdata pointer, so we use
+ * the bus's pci_dev's sysdata instead.
+ */
+ dev->sysdata = tbl;
+
+ return 0;
+
+free_tbl:
+ kfree(tbl);
+done:
+ return ret;
+}
+
+int alloc_tce_table(unsigned int bdf, unsigned long* rootmfn)
+{
+ unsigned int size;
+ dom0_op_t op;
+
+ size = table_size_to_number_of_entries(specified_table_size);
+ size *= PAGE_SIZE;
+
+ /* call into Xen to alloc the table */
+ op.cmd = DOM0_IOMMU_CREATE_IO_SPACE;
+ op.u.iommu_create_io_space.size = size;
+ op.u.iommu_create_io_space.bdf = bdf;
+ op.u.iommu_create_io_space.rootmfn = 0;
+ BUG_ON(HYPERVISOR_dom0_op(&op));
+
+ printk("Calgary: alloc iommu table returned size %Lu bdf 0x%x mfn
0x%Lx\n",
+ op.u.iommu_create_io_space.size,
+ op.u.iommu_create_io_space.bdf,
+ op.u.iommu_create_io_space.rootmfn);
+
+ iommu_detected = 1;
+
+ *rootmfn = op.u.iommu_create_io_space.rootmfn;
+
+ return 0;
+}
diff -Naurp -X /home/muli/w/dontdiff vanilla.xenlinux/arch/x86_64/mm/init-xen.c
xenlinux/arch/x86_64/mm/init-xen.c
--- vanilla.xenlinux/arch/x86_64/mm/init-xen.c 2006-03-16 10:01:19.000000000
+0200
+++ xenlinux/arch/x86_64/mm/init-xen.c 2006-03-16 10:10:02.000000000 +0200
@@ -46,6 +46,7 @@
#include <asm/sections.h>
#include <asm/dma-mapping.h>
#include <asm/swiotlb.h>
+#include <asm/calgary.h>
#include <xen/features.h>
@@ -864,6 +865,8 @@ void __init mem_init(void)
#endif
no_iommu_init();
+ detect_calgary();
+
/* How many end-of-memory variables you have, grandma! */
max_low_pfn = end_pfn;
max_pfn = end_pfn;
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/Documentation/x86_64/boot-options.txt
xenlinux/Documentation/x86_64/boot-options.txt
--- vanilla.xenlinux/Documentation/x86_64/boot-options.txt 2006-03-07
23:11:13.000000000 +0200
+++ xenlinux/Documentation/x86_64/boot-options.txt 2006-03-26
17:21:00.000000000 +0200
@@ -200,6 +200,27 @@ IOMMU
pages Prereserve that many 128K pages for the software IO bounce buffering.
force Force all IO through the software TLB.
+ calgary=[64k,128k,256k,512k,1M,2M,4M,8M]
+ calgary=[translate_empty_slots,translate_phb0]
+
+ 64k,...,8M - Set the size of each PCI slot's translation table
+ when using the Calgary IOMMU. This is the size of the translation
+ table itself in main memory. The smallest table, 64k, covers an IO
+ space of 32MB; the largest, 8MB table, can cover an IO space of
+ 4GB. Normally the kernel will make the right choice by itself.
+
+ translate_empty_slots - Enable translation even on slots that have
+ no devices attached to them, in case a device will be hotplugged
+ in the future.
+
+ translate_phb0 - Enable translation on PHB0. The built-in graphics
+ adapter resides on the first bridge (PHB0); if translation
+ (isolation) is enabled on this PHB, X servers that access the
+ hardware directly from user space might stop working. Enable this
+ option if your X server only accesses hardware through the kernel
+ (or you're not using X) and you wants isolation for this bridge as
+ well.
+
Debugging
oops=panic Always panic on oopses. Default is to just kill the process,
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/include/asm-x86_64/calgary.h
xenlinux/include/asm-x86_64/calgary.h
--- vanilla.xenlinux/include/asm-x86_64/calgary.h 1970-01-01
02:00:00.000000000 +0200
+++ xenlinux/include/asm-x86_64/calgary.h 2006-03-26 21:56:40.000000000
+0200
@@ -0,0 +1,64 @@
+/*
+ * Derived from include/asm-powerpc/iommu.h
+ *
+ * Copyright (C) 2006 Jon Mason <jdmason@xxxxxxxxxx>, IBM Corporation
+ * Copyright (C) 2006 Muli Ben-Yehuda <mulix@xxxxxxxxx>, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_X86_64_CALGARY_H
+#define _ASM_X86_64_CALGARY_H
+
+#include <linux/config.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <asm/types.h>
+
+struct iommu_table {
+ unsigned long it_base; /* mapped address of tce table */
+ unsigned long it_hint; /* Hint for next alloc */
+ unsigned long *it_map; /* A simple allocation bitmap for now */
+ spinlock_t it_lock; /* Protects it_map */
+ unsigned int it_size; /* Size of iommu table in entries */
+ unsigned char it_busno; /* Bus number this table belongs to */
+ void __iomem *bbar;
+ u64 tar_val;
+};
+
+#define TCE_TABLE_SIZE_UNSPECIFIED ~0
+#define TCE_TABLE_SIZE_64K 0
+#define TCE_TABLE_SIZE_128K 1
+#define TCE_TABLE_SIZE_256K 2
+#define TCE_TABLE_SIZE_512K 3
+#define TCE_TABLE_SIZE_1M 4
+#define TCE_TABLE_SIZE_2M 5
+#define TCE_TABLE_SIZE_4M 6
+#define TCE_TABLE_SIZE_8M 7
+
+struct scatterlist;
+struct device_node;
+
+extern void calgary_parse_options(char *);
+extern void iommu_init_table(struct iommu_table *tbl);
+extern int calgary_iommu_init(void);
+
+static inline unsigned int bus_to_phb(unsigned char busno)
+{
+ return ((busno % 15 == 0) ? 0 : busno / 2 + 1);
+}
+
+#endif /* _ASM_X86_64_CALGARY_H */
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/include/asm-x86_64/dma-mapping.h
xenlinux/include/asm-x86_64/dma-mapping.h
--- vanilla.xenlinux/include/asm-x86_64/dma-mapping.h 2006-03-07
23:13:32.000000000 +0200
+++ xenlinux/include/asm-x86_64/dma-mapping.h 2006-03-16 15:18:11.000000000
+0200
@@ -183,5 +183,6 @@ dma_cache_sync(void *vaddr, size_t size,
extern struct device fallback_dev;
extern int panic_on_overflow;
+extern int iommu_detected;
#endif /* _X8664_DMA_MAPPING_H */
diff -Naurp -X /home/muli/w/dontdiff vanilla.xenlinux/include/asm-x86_64/pci.h
xenlinux/include/asm-x86_64/pci.h
--- vanilla.xenlinux/include/asm-x86_64/pci.h 2006-03-07 23:13:32.000000000
+0200
+++ xenlinux/include/asm-x86_64/pci.h 2006-03-05 03:30:12.000000000 +0200
@@ -53,7 +53,7 @@ extern int iommu_setup(char *opt);
*/
#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
-#ifdef CONFIG_GART_IOMMU
+#if defined(CONFIG_GART_IOMMU) || defined(CONFIG_CALGARY_IOMMU)
/*
* x86-64 always supports DAC, but sometimes it is useful to force
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/include/asm-x86_64/proto.h xenlinux/include/asm-x86_64/proto.h
--- vanilla.xenlinux/include/asm-x86_64/proto.h 2006-03-07 23:13:32.000000000
+0200
+++ xenlinux/include/asm-x86_64/proto.h 2006-03-26 17:21:54.000000000 +0200
@@ -104,7 +104,9 @@ extern int unsynchronized_tsc(void);
extern void select_idle_routine(const struct cpuinfo_x86 *c);
extern void gart_parse_options(char *);
-extern void __init no_iommu_init(void);
+extern int gart_iommu_init(void);
+extern void no_iommu_init(void);
+extern void detect_calgary(void);
extern unsigned long table_start, table_end;
diff -Naurp -X /home/muli/w/dontdiff vanilla.xenlinux/include/asm-x86_64/tce.h
xenlinux/include/asm-x86_64/tce.h
--- vanilla.xenlinux/include/asm-x86_64/tce.h 1970-01-01 02:00:00.000000000
+0200
+++ xenlinux/include/asm-x86_64/tce.h 2006-03-16 15:19:05.000000000 +0200
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2006 Muli Ben-Yehuda <mulix@xxxxxxxxx>, IBM Corporation
+ * Copyright (C) 2006 Jon Mason <jdmason@xxxxxxxxxx>, IBM Corporation
+ *
+ * This file is derived from asm-powerpc/tce.h.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_X86_64_TCE_H
+#define _ASM_X86_64_TCE_H
+
+extern void* tce_table_kva[];
+extern unsigned int specified_table_size;
+struct iommu_table;
+
+#define TCE_ENTRY_SIZE 8 /* in bytes */
+
+#define TCE_READ_SHIFT 0
+#define TCE_WRITE_SHIFT 1
+#define TCE_HUBID_SHIFT 2 /* unused */
+#define TCE_RSVD_SHIFT 8 /* unused */
+#define TCE_RPN_SHIFT 12
+#define TCE_UNUSED_SHIFT 48 /* unused */
+
+#define TCE_RPN_MASK 0x0000fffffffff000ULL
+
+extern void tce_build(struct iommu_table *tbl, unsigned long index,
+ unsigned int npages, unsigned long uaddr, int direction);
+extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages);
+extern int alloc_tce_table(unsigned int busnum, unsigned long* rootmfn);
+extern int build_tce_table(struct pci_dev *dev, void __iomem* bbar,
+ unsigned long mfn);
+
+#endif /* _ASM_X86_64_TCE_H */
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/include/xen/interface/dom0_ops.h
xenlinux/include/xen/interface/dom0_ops.h
--- vanilla.xenlinux/include/xen/interface/dom0_ops.h 2006-03-07
23:13:50.000000000 +0200
+++ xenlinux/include/xen/interface/dom0_ops.h 2006-03-07 20:35:40.000000000
+0200
@@ -471,6 +471,20 @@ typedef struct dom0_hypercall_init {
} dom0_hypercall_init_t;
DEFINE_GUEST_HANDLE(dom0_hypercall_init_t);
+#define DOM0_IOMMU_CREATE_IO_SPACE 49
+typedef struct dom0_iommu_create_io_space {
+ u64 size; /* size of the IO address space in bytes */
+ u32 bdf; /* bus/dev/func this space translates for */
+ u64 rootmfn; /* mfn of the root of the iommu table */
+} dom0_iommu_create_io_space_t;
+DEFINE_GUEST_HANDLE(dom0_iommu_create_io_space_t);
+
+#define DOM0_IOMMU_DESTROY_IO_SPACE 50
+typedef struct dom0_iommu_destroy_io_space {
+ u64 rootmfn; /* mfn of the root of the iommu table */
+} dom0_iommu_destroy_io_space_t;
+DEFINE_GUEST_HANDLE(dom0_iommu_destroy_io_space_t);
+
typedef struct dom0_op {
uint32_t cmd;
uint32_t interface_version; /* DOM0_INTERFACE_VERSION */
@@ -512,6 +526,8 @@ typedef struct dom0_op {
struct dom0_irq_permission irq_permission;
struct dom0_iomem_permission iomem_permission;
struct dom0_hypercall_init hypercall_init;
+ struct dom0_iommu_create_io_space iommu_create_io_space;
+ struct dom0_iommu_destroy_io_space iommu_destroy_io_space;
uint8_t pad[128];
} u;
} dom0_op_t;
diff -Naurp -X /home/muli/w/dontdiff
vanilla.xenlinux/include/xen/interface/xen.h
xenlinux/include/xen/interface/xen.h
--- vanilla.xenlinux/include/xen/interface/xen.h 2006-03-16
10:01:19.000000000 +0200
+++ xenlinux/include/xen/interface/xen.h 2006-03-16 23:20:44.000000000
+0200
@@ -60,6 +60,8 @@
#define __HYPERVISOR_acm_op 27
#define __HYPERVISOR_nmi_op 28
#define __HYPERVISOR_sched_op_new 29
+#define __HYPERVISOR_iommu_map 30
+#define __HYPERVISOR_iommu_unmap 31
/*
* VIRTUAL INTERRUPTS
--
Muli Ben-Yehuda
http://www.mulix.org | http://mulix.livejournal.com/
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel
|
Home