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xen-devel
[Xen-devel] Re: Genapic testing
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To: |
"Puthiyaparambil, Aravindh" <aravindh.puthiyaparambil@xxxxxxxxxx> |
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Subject: |
[Xen-devel] Re: Genapic testing |
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From: |
Keir Fraser <Keir.Fraser@xxxxxxxxxxxx> |
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Date: |
Tue, 31 May 2005 19:24:25 +0100 |
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Cc: |
xen-devel@xxxxxxxxxxxxxxxxxxx, "Davis, Jason" <jason.davis@xxxxxxxxxx>, "Vessey, Bruce A" <Bruce.Vessey@xxxxxxxxxx>, "Subrahmanian, Raj" <raj.subrahmanian@xxxxxxxxxx> |
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Tue, 31 May 2005 18:27:10 +0000 |
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On 26 May 2005, at 21:52, Puthiyaparambil, Aravindh wrote:
Are the TSCs on all CPUs suitably sync'ed up? If the PIT is firing and
we are updating our timestamp info often enough, and all CPUs have
similar TSC values, then all should work okay. Don Fry has a patch
that
handles unsync'ed TSCs, if that turns out to be the problem.
On native Linux the skew is reported and is "fixed up". But that does
not mean the TSC was really adjusted, it will keep running with this
gap. So the CPU TSC skew could be the problem. The only difference is
that for Xen, the skew for the boot CPU is unusually high.
Aravindh,
I noticed yesterday that I was missing a call to enable_apic_mode()
during local APIC initialisation. On es7000 this does some cryptic
twiddling that I don't understand, but I suppose could arbitrarily
break something important. :-)
I've now fixed this omission so it is probably worth trying to boot on
es7000 and see if the timer problems have disappeared.
-- Keir
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