[Xen-changelog] [xen-4.0-testing] x86, amd, MTRR: correct DramModEn bit of SYS_CFG MSR

[Xen patchbot-4.0-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Wei Huang <wei.huang2@xxxxxxx>
# Date 1302187459 -3600
# Node ID 72e213aa6425481b1cbacff45c480fa8b1f46c67
# Parent  ab11156d606bfae77499067faf6f653a858c10d5
x86, amd, MTRR: correct DramModEn bit of SYS_CFG MSR

Some buggy BIOS might set SYS_CFG DramModEn bit to 1, which can cause
unexpected behavior on AMD platforms. This patch clears DramModEn bit
if it is 1.

Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>
xen-unstable changeset:   23153:8fb61c9ebe49
xen-unstable date:        Wed Apr 06 09:01:31 2011 +0100
---


diff -r ab11156d606b -r 72e213aa6425 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Thu Apr 07 15:42:16 2011 +0100
+++ b/xen/arch/x86/cpu/amd.c    Thu Apr 07 15:44:19 2011 +0100
@@ -347,6 +347,32 @@
                on_each_cpu(disable_c1e, NULL, 1);
 }
 
+/*
+ * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG : 
+ * "The MtrrFixDramModEn bit should be set to 1 during BIOS initalization of 
+ * the fixed MTRRs, then cleared to 0 for operation."
+ */
+static void check_syscfg_dram_mod_en(void)
+{
+       uint64_t syscfg;
+       static bool_t printed = 0;
+
+       if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+               (boot_cpu_data.x86 >= 0x0f)))
+               return;
+
+       rdmsrl(MSR_K8_SYSCFG, syscfg);
+       if (!(syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY))
+               return;
+
+       if (!test_and_set_bool(printed))
+               printk(KERN_ERR "MTRR: SYSCFG[MtrrFixDramModEn] not "
+                       "cleared by BIOS, clearing this bit\n");
+
+       syscfg &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
+       wrmsrl(MSR_K8_SYSCFG, syscfg);
+}
+
 static void __devinit init_amd(struct cpuinfo_x86 *c)
 {
        u32 l, h;
@@ -624,6 +650,8 @@
 
        set_cpuidmask(c);
 
+       check_syscfg_dram_mod_en();
+
        start_svm(c);
 }
 

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