# HG changeset patch
# User Liu, Jinsong <jinsong.liu@xxxxxxxxx>
# Date 1299863933 0
# Node ID fb39508881540f3dec0f24fd4d81e8234b4fbed6
# Parent 552c3059264e1a4c9cebf22277ae1232f59c863e
x86: Fix cpu offline bug: add clflush inside dead loop
At some platform (like Xen 7400), when hyperthreading, an offlined
thread may waked spuriously up by its brother, and returning around
the loop. This patch explicitly clflush the cache line in a light
weight way to workaround potential issue. Unlike wbinvd, clflush is
not serializing instruction, hence memory fence is necessary to make
sure all load/store operation visible before flush cache line.
Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
---
diff -r 552c3059264e -r fb3950888154 xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c Fri Mar 11 17:18:01 2011 +0000
+++ b/xen/arch/x86/acpi/cpu_idle.c Fri Mar 11 17:18:53 2011 +0000
@@ -554,6 +554,7 @@
{
struct acpi_processor_power *power;
struct acpi_processor_cx *cx;
+ void *mwait_ptr;
if ( (power = processor_powers[smp_processor_id()]) == NULL )
goto default_halt;
@@ -561,23 +562,33 @@
if ( (cx = &power->states[power->count-1]) == NULL )
goto default_halt;
- /*
- * cache must be flashed as the last ops before cpu going into dead,
- * otherwise, cpu may dead with dirty data breaking cache coherency,
- * leading to strange errors.
- */
- wbinvd();
- for ( ; ; )
+ mwait_ptr = (void *)&mwait_wakeup(smp_processor_id());
+
+ if ( cx->entry_method == ACPI_CSTATE_EM_FFH )
{
- switch ( cx->entry_method )
+ /*
+ * cache must be flashed as the last ops before cpu going into dead,
+ * otherwise, cpu may dead with dirty data breaking cache coherency,
+ * leading to strange errors.
+ */
+ wbinvd();
+
+ while ( 1 )
{
- case ACPI_CSTATE_EM_FFH:
- /* Not treat interrupt as break event */
- __monitor((void *)&mwait_wakeup(smp_processor_id()), 0, 0);
- __mwait(cx->address, 0);
- break;
- default:
- goto default_halt;
+ /*
+ * 1. The CLFLUSH is a workaround for erratum AAI65 for
+ * the Xeon 7400 series.
+ * 2. The WBINVD is insufficient due to the spurious-wakeup
+ * case where we return around the loop.
+ * 3. Unlike wbinvd, clflush is a light weight but not serializing
+ * instruction, hence memory fence is necessary to make sure all
+ * load/store visible before flush cache line.
+ */
+ mb();
+ clflush(mwait_ptr);
+ __monitor(mwait_ptr, 0, 0);
+ mb();
+ __mwait(cx->address, 0);
}
}
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