[Xen-changelog] [xen-unstable] x86: Do not expose XSAVE/AVX to guests.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1288888187 0
# Node ID d508b18a68447f91cd879b79a498f06536d89f8e
# Parent  e72bd79b53511a173c7d7a38b8d77ff16ec7868b
x86: Do not expose XSAVE/AVX to guests.

Signed-off-by: Keir Fraser <keir@xxxxxxx>
---
 tools/libxc/xc_cpuid_x86.c |    4 ++--
 xen/arch/x86/traps.c       |    1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff -r e72bd79b5351 -r d508b18a6844 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c        Thu Nov 04 16:25:26 2010 +0000
+++ b/tools/libxc/xc_cpuid_x86.c        Thu Nov 04 16:29:47 2010 +0000
@@ -195,8 +195,7 @@ static void xc_cpuid_hvm_policy(
                     bitmaskof(X86_FEATURE_SSE4_1) |
                     bitmaskof(X86_FEATURE_SSE4_2) |
                     bitmaskof(X86_FEATURE_POPCNT) |
-                    bitmaskof(X86_FEATURE_AES) |
-                    bitmaskof(X86_FEATURE_AVX));
+                    bitmaskof(X86_FEATURE_AES));
 
         regs[2] |= bitmaskof(X86_FEATURE_HYPERVISOR);
 
@@ -324,6 +323,7 @@ static void xc_cpuid_pv_policy(
         clear_bit(X86_FEATURE_XTPR, regs[2]);
         clear_bit(X86_FEATURE_PDCM, regs[2]);
         clear_bit(X86_FEATURE_DCA, regs[2]);
+        clear_bit(X86_FEATURE_XSAVE, regs[2]);
         set_bit(X86_FEATURE_HYPERVISOR, regs[2]);
         break;
     case 0x80000001:
diff -r e72bd79b5351 -r d508b18a6844 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Thu Nov 04 16:25:26 2010 +0000
+++ b/xen/arch/x86/traps.c      Thu Nov 04 16:29:47 2010 +0000
@@ -795,6 +795,7 @@ static void pv_cpuid(struct cpu_user_reg
         __clear_bit(X86_FEATURE_XTPR % 32, &c);
         __clear_bit(X86_FEATURE_PDCM % 32, &c);
         __clear_bit(X86_FEATURE_DCA % 32, &c);
+        __clear_bit(X86_FEATURE_XSAVE % 32, &c);
         if ( !cpu_has_apic )
            __clear_bit(X86_FEATURE_X2APIC % 32, &c);
         __set_bit(X86_FEATURE_HYPERVISOR % 32, &c);

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