# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1279284884 -3600
# Node ID 12f0618400de62279bc9b111c4e2ad73e1673ca1
# Parent fedab6367c9a0141d49853c77a23d6642ba70ff6
x86: use cpuid vector 0xb when available for detecting cpu topology
cpuid leaf 0xb provides extended topology enumeration. This interface
provides the 32-bit x2APIC id of the logical processor and it also
provides a new mechanism to detect SMT and core siblings (which
provides increased addressability).
Signed-off-by: Weidong Han <weidong.han@xxxxxxxxx>
---
xen/arch/x86/cpu/common.c | 79 ++++++++++++++++++++++++++++++++++++++-
xen/arch/x86/cpu/intel.c | 13 ++++--
xen/include/asm-x86/cpufeature.h | 1
xen/include/asm-x86/processor.h | 2
4 files changed, 89 insertions(+), 6 deletions(-)
diff -r fedab6367c9a -r 12f0618400de xen/arch/x86/cpu/common.c
--- a/xen/arch/x86/cpu/common.c Fri Jul 16 13:52:18 2010 +0100
+++ b/xen/arch/x86/cpu/common.c Fri Jul 16 13:54:44 2010 +0100
@@ -469,7 +469,6 @@ void __cpuinit identify_cpu(struct cpuin
mtrr_bp_init();
}
-#ifdef CONFIG_X86_HT
/* cpuid returns the value latched in the HW at reset, not the APIC ID
* register's value. For any box whose BIOS changes APIC IDs, like
* clustered APIC systems, we must use hard_smp_processor_id.
@@ -481,6 +480,81 @@ static inline u32 phys_pkg_id(u32 cpuid_
return hard_smp_processor_id() >> index_msb;
}
+/* leaf 0xb SMT level */
+#define SMT_LEVEL 0
+
+/* leaf 0xb sub-leaf types */
+#define INVALID_TYPE 0
+#define SMT_TYPE 1
+#define CORE_TYPE 2
+
+#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
+#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
+#define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
+
+/*
+ * Check for extended topology enumeration cpuid leaf 0xb and if it
+ * exists, use it for cpu topology detection.
+ */
+void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
+{
+ unsigned int eax, ebx, ecx, edx, sub_index;
+ unsigned int ht_mask_width, core_plus_mask_width;
+ unsigned int core_select_mask, core_level_siblings, smp_num_siblings;
+ unsigned int initial_apicid;
+ int cpu = smp_processor_id();
+
+ if ( c->cpuid_level < 0xb )
+ return;
+
+ cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
+
+ /* Check if the cpuid leaf 0xb is actually implemented */
+ if ( ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE) )
+ return;
+
+ set_bit(X86_FEATURE_XTOPOLOGY, c->x86_capability);
+
+ initial_apicid = edx;
+
+ /* Populate HT related information from sub-leaf level 0 */
+ core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
+ core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
+
+ sub_index = 1;
+ do {
+ cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
+
+ /* Check for the Core type in the implemented sub leaves */
+ if ( LEAFB_SUBTYPE(ecx) == CORE_TYPE ) {
+ core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
+ core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
+ break;
+ }
+
+ sub_index++;
+ } while ( LEAFB_SUBTYPE(ecx) != INVALID_TYPE );
+
+ core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
+
+ cpu_core_id[cpu] = phys_pkg_id(initial_apicid, ht_mask_width)
+ & core_select_mask;
+ phys_proc_id[cpu] = phys_pkg_id(initial_apicid, core_plus_mask_width);
+
+ c->apicid = phys_pkg_id(initial_apicid, 0);
+ c->x86_max_cores = (core_level_siblings / smp_num_siblings);
+
+ if ( opt_cpu_info )
+ {
+ printk("CPU: Physical Processor ID: %d\n",
+ phys_proc_id[cpu]);
+ if ( c->x86_max_cores > 1 )
+ printk("CPU: Processor Core ID: %d\n",
+ cpu_core_id[cpu]);
+ }
+}
+
+#ifdef CONFIG_X86_HT
void __cpuinit detect_ht(struct cpuinfo_x86 *c)
{
u32 eax, ebx, ecx, edx;
@@ -491,7 +565,8 @@ void __cpuinit detect_ht(struct cpuinfo_
c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
- if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
+ if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)
+ || cpu_has(c, X86_FEATURE_XTOPOLOGY))
return;
c->x86_num_siblings = (ebx & 0xff0000) >> 16;
diff -r fedab6367c9a -r 12f0618400de xen/arch/x86/cpu/intel.c
--- a/xen/arch/x86/cpu/intel.c Fri Jul 16 13:52:18 2010 +0100
+++ b/xen/arch/x86/cpu/intel.c Fri Jul 16 13:54:44 2010 +0100
@@ -154,6 +154,9 @@ static void __devinit init_intel(struct
}
#endif
+ /* Detect the extended topology information if available */
+ detect_extended_topology(c);
+
select_idle_routine(c);
l2 = init_intel_cacheinfo(c);
if (c->cpuid_level > 9) {
@@ -197,10 +200,12 @@ static void __devinit init_intel(struct
if ( p )
safe_strcpy(c->x86_model_id, p);
-
- c->x86_max_cores = num_cpu_cores(c);
-
- detect_ht(c);
+
+ if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
+ {
+ c->x86_max_cores = num_cpu_cores(c);
+ detect_ht(c);
+ }
set_cpuidmask(c);
diff -r fedab6367c9a -r 12f0618400de xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Fri Jul 16 13:52:18 2010 +0100
+++ b/xen/include/asm-x86/cpufeature.h Fri Jul 16 13:54:44 2010 +0100
@@ -78,6 +78,7 @@
#define X86_FEATURE_ARAT (3*32+ 10) /* Always running APIC timer */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_TSC_RELIABLE (3*32+12) /* TSC is known to be reliable */
+#define X86_FEATURE_XTOPOLOGY (3*32+13) /* cpu topology enum extensions */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
diff -r fedab6367c9a -r 12f0618400de xen/include/asm-x86/processor.h
--- a/xen/include/asm-x86/processor.h Fri Jul 16 13:52:18 2010 +0100
+++ b/xen/include/asm-x86/processor.h Fri Jul 16 13:54:44 2010 +0100
@@ -201,6 +201,8 @@ extern void print_cpu_info(unsigned int
extern void print_cpu_info(unsigned int cpu);
extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
extern void dodgy_tsc(void);
+
+extern void detect_extended_topology(struct cpuinfo_x86 *c);
#ifdef CONFIG_X86_HT
extern void detect_ht(struct cpuinfo_x86 *c);
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