# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1279041213 -3600
# Node ID f72879804eb083dec369f450d35ba8a16a1ad020
# Parent a3a55a6e47610192b44f88282aacefe481b3471a
[IOMMU] Debug info for AMD IOMMU event log
Print out the event log entry content for debug purposes.
Additionally, when IOMMU reset event log (due to event log overflow),
we should print out the event log content for debugging.
Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>
Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
---
xen/drivers/passthrough/amd/iommu_init.c | 80 +++++++++++++++++--------------
1 files changed, 44 insertions(+), 36 deletions(-)
diff -r a3a55a6e4761 -r f72879804eb0 xen/drivers/passthrough/amd/iommu_init.c
--- a/xen/drivers/passthrough/amd/iommu_init.c Tue Jul 13 18:12:15 2010 +0100
+++ b/xen/drivers/passthrough/amd/iommu_init.c Tue Jul 13 18:13:33 2010 +0100
@@ -270,6 +270,42 @@ static void set_iommu_event_log_control(
writel(entry, iommu->mmio_base + IOMMU_CONTROL_MMIO_OFFSET);
}
+static void parse_event_log_entry(u32 entry[]);
+
+static int amd_iommu_read_event_log(struct amd_iommu *iommu)
+{
+ u32 tail, head, *event_log;
+
+ BUG_ON( !iommu );
+
+ /* make sure there's an entry in the log */
+ tail = readl(iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
+ tail = get_field_from_reg_u32(tail,
+ IOMMU_EVENT_LOG_TAIL_MASK,
+ IOMMU_EVENT_LOG_TAIL_SHIFT);
+
+ while ( tail != iommu->event_log_head )
+ {
+ /* read event log entry */
+ event_log = (u32 *)(iommu->event_log.buffer +
+ (iommu->event_log_head *
+ IOMMU_EVENT_LOG_ENTRY_SIZE));
+
+ parse_event_log_entry(event_log);
+
+ if ( ++iommu->event_log_head == iommu->event_log.entries )
+ iommu->event_log_head = 0;
+
+ /* update head pointer */
+ set_field_in_reg_u32(iommu->event_log_head, 0,
+ IOMMU_EVENT_LOG_HEAD_MASK,
+ IOMMU_EVENT_LOG_HEAD_SHIFT, &head);
+ writel(head, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+ }
+
+ return 0;
+}
+
static void amd_iommu_reset_event_log(struct amd_iommu *iommu)
{
u32 entry;
@@ -294,6 +330,9 @@ static void amd_iommu_reset_event_log(st
set_iommu_event_log_control(iommu, IOMMU_CONTROL_DISABLED);
+ /* read event log for debugging */
+ amd_iommu_read_event_log(iommu);
+
/*clear overflow bit */
set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, entry,
IOMMU_STATUS_EVENT_OVERFLOW_MASK,
@@ -304,42 +343,6 @@ static void amd_iommu_reset_event_log(st
iommu->event_log_head = 0;
set_iommu_event_log_control(iommu, IOMMU_CONTROL_ENABLED);
-}
-
-static void parse_event_log_entry(u32 entry[]);
-
-static int amd_iommu_read_event_log(struct amd_iommu *iommu)
-{
- u32 tail, head, *event_log;
-
- BUG_ON( !iommu );
-
- /* make sure there's an entry in the log */
- tail = readl(iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
- tail = get_field_from_reg_u32(tail,
- IOMMU_EVENT_LOG_TAIL_MASK,
- IOMMU_EVENT_LOG_TAIL_SHIFT);
-
- while ( tail != iommu->event_log_head )
- {
- /* read event log entry */
- event_log = (u32 *)(iommu->event_log.buffer +
- (iommu->event_log_head *
- IOMMU_EVENT_LOG_ENTRY_SIZE));
-
- parse_event_log_entry(event_log);
-
- if ( ++iommu->event_log_head == iommu->event_log.entries )
- iommu->event_log_head = 0;
-
- /* update head pointer */
- set_field_in_reg_u32(iommu->event_log_head, 0,
- IOMMU_EVENT_LOG_HEAD_MASK,
- IOMMU_EVENT_LOG_HEAD_SHIFT, &head);
- writel(head, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
- }
-
- return 0;
}
static void iommu_msi_set_affinity(unsigned int irq, cpumask_t mask)
@@ -492,6 +495,11 @@ static void parse_event_log_entry(u32 en
"%s: domain:%d, device id:0x%x, fault address:0x%"PRIx64"\n",
event_str[code-1], domain_id, device_id, *addr);
}
+ else
+ {
+ AMD_IOMMU_DEBUG("event 0x%08x 0x%08x 0x%08x 0x%08x\n", entry[0],
+ entry[1], entry[2], entry[3]);
+ }
}
static void amd_iommu_page_fault(int irq, void *dev_id,
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