[Xen-changelog] [xen-unstable] vmx: Fix bug in VMX VPMU fixed function PMC offset

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1277110750 -3600
# Node ID 31708477f0a92be70a940d1c8ff1aa721051bba8
# Parent  46a4c936b77e483971d2b3eb0b544c61700f824a
vmx: Fix bug in VMX VPMU fixed function PMC offset

This is a minor fix to the calculation of bit-width of fixed function
perfmon counters in Intel processors.  Bits 5-12 of edx register
should be calculated as (edx & 0x1fe0) >>5 instead of using 0x1f70.

From: "John, Jaiber J" <jaiber.j.john@xxxxxxxxx>
Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vpmu_core2.c |    2 +-
 1 files changed, 1 insertion(+), 1 deletion(-)

diff -r 46a4c936b77e -r 31708477f0a9 xen/arch/x86/hvm/vmx/vpmu_core2.c
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c Mon Jun 21 09:58:17 2010 +0100
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c Mon Jun 21 09:59:10 2010 +0100
@@ -83,7 +83,7 @@ static int core2_get_bitwidth_fix_count(
 {
     u32 eax, ebx, ecx, edx;
     cpuid(0xa, &eax, &ebx, &ecx, &edx);
-    return ((edx & 0x1f70) >> 5);
+    return ((edx & 0x1fe0) >> 5);
 }
 
 static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)

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