# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1276604494 -3600
# Node ID 1aeecd35f4f4ebf97b4334a60692512251c758ba
# Parent b0f7f710f512aba0fca814467e4f5fe7b906ada3
x86/mce: assorted fixes
- correct various range checks (avoids bogus warnings on domains
modifying virtualized MSRs)
- correct consistency check (so that APs get checked instead of the
BP [against uninitialized data])
- reduce verbosity (capabilities printed only once, but then all of
the relevant values)
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
xen/arch/x86/cpu/mcheck/mce.h | 5 ++---
xen/arch/x86/cpu/mcheck/mce_intel.c | 34 ++++++++++++++++------------------
2 files changed, 18 insertions(+), 21 deletions(-)
diff -r b0f7f710f512 -r 1aeecd35f4f4 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h Tue Jun 15 13:21:03 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.h Tue Jun 15 13:21:34 2010 +0100
@@ -174,15 +174,14 @@ static inline int mce_vendor_bank_msr(ui
static inline int mce_vendor_bank_msr(uint32_t msr)
{
if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- (msr > MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks)) )
+ msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks) )
return 1;
return 0;
}
static inline int mce_bank_msr(uint32_t msr)
{
- if ( (msr > MSR_IA32_MC0_CTL2 &&
- msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) ||
+ if ( (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(nr_mce_banks)) ||
mce_vendor_bank_msr(msr) )
return 1;
return 0;
diff -r b0f7f710f512 -r 1aeecd35f4f4 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c Tue Jun 15 13:21:03 2010 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c Tue Jun 15 13:21:34 2010 +0100
@@ -1146,26 +1146,26 @@ static void intel_init_mca(struct cpuinf
first = mce_firstbank(c);
- dprintk(XENLOG_INFO, "MCA Capaility: CPU %x SER %x"
- "CMCI %x firstbank %x extended MCE MSR %x\n",
- smp_processor_id(), ser, cmci, first, ext_num);
-
- if (smp_processor_id())
- {
+ if (smp_processor_id() == 0)
+ {
+ dprintk(XENLOG_INFO, "MCA Capability: BCAST %x SER %x"
+ " CMCI %x firstbank %x extended MCE MSR %x\n",
+ broadcast, ser, cmci, first, ext_num);
+
mce_broadcast = broadcast;
cmci_support = cmci;
ser_support = ser;
nr_intel_ext_msrs = ext_num;
firstbank = first;
}
- else
- {
- if (cmci != cmci_support || ser != ser_support ||
- broadcast != mce_broadcast ||
- first != firstbank)
- dprintk(XENLOG_WARNING,
- "CPU %x has different MCA capability with BSP\n"
- "may cause undetermined result!!!\n", smp_processor_id());
+ else if (cmci != cmci_support || ser != ser_support ||
+ broadcast != mce_broadcast ||
+ first != firstbank || ext_num != nr_intel_ext_msrs)
+ {
+ dprintk(XENLOG_WARNING,
+ "CPU %u has different MCA capability (%x,%x,%x,%x,%x)"
+ " than BSP, may cause undetermined result!!!\n",
+ smp_processor_id(), broadcast, ser, cmci, first, ext_num);
}
}
@@ -1265,8 +1265,7 @@ int intel_mce_wrmsr(uint32_t msr, uint64
{
int ret = 0;
- if (msr > MSR_IA32_MC0_CTL2 &&
- msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))
+ if (msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))
{
mce_printk(MCE_QUIET, "We have disabled CMCI capability, "
"Guest should not write this MSR!\n");
@@ -1280,8 +1279,7 @@ int intel_mce_rdmsr(uint32_t msr, uint64
{
int ret = 0;
- if (msr > MSR_IA32_MC0_CTL2 &&
- msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))
+ if (msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))
{
mce_printk(MCE_QUIET, "We have disabled CMCI capability, "
"Guest should not read this MSR!\n");
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