# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1249972586 -3600
# Node ID e35a1c004fc22ba4a38e0ea53c272f89b0256c51
# Parent 01fe7054b335434f1b8df08bc18c884b4fdaba4b
xentrace: fix "%016x" format
xentrace_format cannot use "0x016x" format as we expect.
It show only %(N) as "0x016x" format, not as "%(N+1)08x%(N)08x".
So I fixed tools/xentrace/formats by using "%(N+1)08x%(N)08x" format.
Also I added some TRC_PV entries.
Signed-off-by: Akio Takebe <takebe_akio@xxxxxxxxxxxxxx>
---
tools/xentrace/formats | 83 +++++++++++++++++++++++++++----------------------
1 files changed, 46 insertions(+), 37 deletions(-)
diff -r 01fe7054b335 -r e35a1c004fc2 tools/xentrace/formats
--- a/tools/xentrace/formats Tue Aug 11 07:34:55 2009 +0100
+++ b/tools/xentrace/formats Tue Aug 11 07:36:26 2009 +0100
@@ -1,4 +1,4 @@ 0x00000000 CPU%(cpu)d %(tsc)d (+%(relt
-0x00000000 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) unknown (0x%(event)016x) [
0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x ]
+0x00000000 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) unknown (0x%(event)016x) [
0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x 0x%(6)08x 0x%(7)08x ]
0x0001f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) lost_records 0x%(1)08x
0x0001f002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) wrap_buffer 0x%(1)08x
@@ -36,24 +36,24 @@ 0x0002800f CPU%(cpu)d %(tsc)d (+%(relt
0x00081001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) VMENTRY
0x00081002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) VMEXIT [ exitcode =
0x%(1)08x, rIP = 0x%(2)08x ]
-0x00081102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) VMEXIT [ exitcode =
0x%(1)08x, rIP = 0x%(2)016x ]
+0x00081102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) VMEXIT [ exitcode =
0x%(1)08x, rIP = 0x%(3)08x%(2)08x ]
0x00082001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_XEN [ errorcode =
0x%(2)02x, virt = 0x%(1)08x ]
-0x00082101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_XEN [ errorcode =
0x%(2)02x, virt = 0x%(1)016x ]
+0x00082101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_XEN [ errorcode =
0x%(3)02x, virt = 0x%(2)08x%(1)08x ]
0x00082002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_INJECT [ errorcode =
0x%(1)02x, virt = 0x%(2)08x ]
-0x00082102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_INJECT [ errorcode =
0x%(1)02x, virt = 0x%(2)016x ]
+0x00082102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) PF_INJECT [ errorcode =
0x%(1)02x, virt = 0x%(3)08x%(2)08x ]
0x00082003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INJ_EXC [ vector =
0x%(1)02x, errorcode = 0x%(2)04x ]
0x00082004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INJ_VIRQ [ vector =
0x%(1)02x, fake = %(2)d ]
0x00082005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) REINJ_VIRQ [ vector =
0x%(1)02x ]
0x00082006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) IO_READ [ port =
0x%(1)04x, size = %(2)d ]
0x00082007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) IO_WRITE [ port =
0x%(1)04x, size = %(2)d ]
0x00082008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_READ [ CR# = %(1)d,
value = 0x%(2)08x ]
-0x00082108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_READ [ CR# = %(1)d,
value = 0x%(2)016x ]
+0x00082108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_READ [ CR# = %(1)d,
value = 0x%(3)08x%(2)08x ]
0x00082009 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_WRITE [ CR# = %(1)d,
value = 0x%(2)08x ]
-0x00082109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_WRITE [ CR# = %(1)d,
value = 0x%(2)016x ]
+0x00082109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CR_WRITE [ CR# = %(1)d,
value = 0x%(3)08x%(2)08x ]
0x0008200A CPU%(cpu)d %(tsc)d (+%(reltsc)8d) DR_READ
0x0008200B CPU%(cpu)d %(tsc)d (+%(reltsc)8d) DR_WRITE
-0x0008200C CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MSR_READ [ MSR# =
0x%(1)08x, value = 0x%(2)016x ]
-0x0008200D CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MSR_WRITE [ MSR# =
0x%(1)08x, value = 0x%(2)016x ]
+0x0008200C CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MSR_READ [ MSR# =
0x%(1)08x, value = 0x%(3)08x%(2)08x ]
+0x0008200D CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MSR_WRITE [ MSR# =
0x%(1)08x, value = 0x%(3)08x%(2)08x ]
0x0008200E CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CPUID [ func =
0x%(1)08x, eax = 0x%(2)08x, ebx = 0x%(3)08x, ecx=0x%(4)08x, edx = 0x%(5)08x ]
0x0008200F CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INTR [ vector =
0x%(1)02x ]
0x00082010 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) NMI
@@ -61,7 +61,7 @@ 0x00082012 CPU%(cpu)d %(tsc)d (+%(relt
0x00082012 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) VMMCALL [ func = 0x%(1)08x
]
0x00082013 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) HLT [ intpending =
%(1)d ]
0x00082014 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INVLPG [ is invlpga? =
%(1)d, virt = 0x%(2)08x ]
-0x00082114 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INVLPG [ is invlpga? =
%(1)d, virt = 0x%(2)016x ]
+0x00082114 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) INVLPG [ is invlpga? =
%(1)d, virt = 0x%(3)08x%(2)08x ]
0x00082015 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MCE
0x00082016 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) IOPORT_READ [ data = 0x%(1)04x
]
0x00082216 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) IOPORT_WRITE [ data =
0x%(1)04x ]
@@ -69,56 +69,65 @@ 0x00082217 CPU%(cpu)d %(tsc)d (+%(relt
0x00082217 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) MMIO_WRITE [ data = 0x%(1)04x
]
0x00082018 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) CLTS
0x00082019 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) LMSW [ value =
0x%(1)08x ]
-0x00082119 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) LMSW [ value =
0x%(1)016x ]
+0x00082119 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) LMSW [ value =
0x%(2)08x%(1)08x ]
0x0010f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_grant_map [ domid =
%(1)d ]
0x0010f002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_grant_unmap [ domid =
%(1)d ]
0x0010f003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_grant_transfer [ domid =
%(1)d ]
0x0020f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ eip = 0x%(1)08x,
eax = 0x%(2)08x ]
-0x0020f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ rip = 0x%(1)016x,
eax = 0x%(2)08x ]
+0x0020f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) hypercall [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
0x0020f003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ eip = 0x%(1)08x,
trapnr:error = 0x%(2)08x ]
-0x0020f103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ rip = 0x%(1)016x,
trapnr:error = 0x%(2)08x ]
+0x0020f103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) trap [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
0x0020f004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ eip = 0x%(1)08x,
addr = 0x%(2)08x, error = 0x%(3)08x ]
-0x0020f104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ rip = 0x%(1)16x,
addr = 0x%(3)16x, error = 0x%(5)08x ]
+0x0020f104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
+0x0020f005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ eip =
0x%(1)08x ]
+0x0020f105 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) forced_invalid_op [ rip =
0x%(2)08x%(1)08x ]
+0x0020f006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ eip =
0x%(1)08x ]
+0x0020f106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ rip =
0x%(2)08x%(1)08x ]
+0x0020f007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ eip =
0x%(1)08x ]
+0x0020f107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ rip =
0x%(2)08x%(1)08x ]
+0x0020f008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
+0x0020f108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) math_state_restore
+0x0020f009 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ eip =
0x%(1)08x, addr = 0x%(2)08x ]
+0x0020f109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) paging_fixup [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
+0x0020f00a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ eip =
0x%(1)08x, offset = 0x%(2)08x ]
+0x0020f10a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) gdt_ldt_mapping_fault [ rip =
0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
+0x0020f00b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f10b CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f00c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f10c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
-0x0020f006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ eip =
0x%(1)08x ]
-0x0020f106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_privop [ rip =
0x%(1)16x ]
-0x0020f007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ eip =
0x%(1)08x ]
-0x0020f107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) emulate_4G [ rip =
0x%(1)16x ]
-0x0020f00c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
0x%(2)08x, eip = 0x%(1)08x, npte = 0x%(1)16x ]
-0x0020f10c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) ptwr_emulation_pae [ addr =
0x%(2)16x, rip = 0x%(1)16x, npte = 0x%(1)16x ]
-
-0x0040f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
[ gl1e = 0x%(1)16x, va = 0x%(2)08x, flags = 0x%(3)08x ]
-0x0040f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
[ gl1e = 0x%(1)16x, va = 0x%(2)16x, flags = 0x%(3)08x ]
+0x0040f001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(3)08x, flags = 0x%(4)08x ]
+0x0040f101 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_not_shadow
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(5)08x ]
0x0040f002 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_propagate
[ va = 0x%(1)08x ]
-0x0040f102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_propagate
[ va = 0x%(1)16x ]
+0x0040f102 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_propagate
[ va = 0x%(2)08x%(1)08x ]
0x0040f003 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_mmio
[ va = 0x%(1)08x ]
-0x0040f103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_mmio
[ va = 0x%(1)16x ]
+0x0040f103 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fast_mmio
[ va = 0x%(2)08x%(1)08x ]
0x0040f004 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_false_fast_path
[ va = 0x%(1)08x ]
-0x0040f104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_false_fast_path
[ va = 0x%(1)16x ]
+0x0040f104 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_false_fast_path
[ va = 0x%(2)08x%(1)08x ]
0x0040f005 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_mmio
[ va = 0x%(1)08x ]
-0x0040f105 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_mmio
[ va = 0x%(1)16x ]
+0x0040f105 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_mmio
[ va = 0x%(2)08x%(1)08x ]
0x0040f006 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fixup
[ gl1e = 0x%(1)08x, va = 0x%(2)08x, flags = 0x%(3)08x ]
-0x0040f106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fixup
[ gl1e = 0x%(1)16x, va = 0x%(2)16x, flags = 0x%(3)08x ]
+0x0040f106 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_fixup
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(3)08x ]
0x0040f007 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_domf_dying
[ va = 0x%(1)08x ]
-0x0040f107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_domf_dying
[ va = 0x%(1)16x ]
-0x0040f008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate
[ gl1e = 0x%(1)08x, write_val = 0x%(2)08x, va = 0x%(3)08x, flags =
0x%(4)08x, emulation_count = 0x%(5)08x]
-0x0040f108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate
[ gl1e = 0x%(1)16x, write_val = 0x%(2)16x, va = 0x%(3)16x, flags =
0x%(4)08x, emulation_count = 0x%(5)08x]
+0x0040f107 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_domf_dying
[ va = 0x%(2)08x%(1)08x ]
+0x0040f008 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate
[ gl1e = 0x%(1)08x, write_val = 0x%(2)08x, va = 0x%(3)08x, flags = 0x%(4)08x
]
+0x0040f108 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate
[ gl1e = 0x%(2)08x%(1)08x, write_val = 0x%(4)08x%(3)08x, va =
0x%(6)08x%(5)08x, flags = 0x%(7)08x ]
0x0040f009 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_user
[ va = 0x%(1)08x, gfn = 0x%(2)08x ]
-0x0040f109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_user
[ va = 0x%(1)16x, gfn = 0x%(2)16x ]
+0x0040f109 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_user
[ va = 0x%(2)08x%(1)08x, gfn = 0x%(4)08x%(3)08x ]
0x0040f00a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_evtinj
[ va = 0x%(1)08x, gfn = 0x%(2)08x ]
-0x0040f10a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_evtinj
[ va = 0x%(1)16x, gfn = 0x%(2)16x ]
+0x0040f10a CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_unshadow_evtinj
[ va = 0x%(2)08x%(1)08x, gfn = 0x%(4)08x%(3)08x ]
0x0040f00b CPU%(cpu)d %(tsc)d (+%(reltsc)8d)
shadow_emulate_unshadow_unhandled [ va = 0x%(1)08x, gfn = 0x%(2)08x ]
-0x0040f10b CPU%(cpu)d %(tsc)d (+%(reltsc)8d)
shadow_emulate_unshadow_unhandled [ va = 0x%(1)16x, gfn = 0x%(2)16x ]
+0x0040f10b CPU%(cpu)d %(tsc)d (+%(reltsc)8d)
shadow_emulate_unshadow_unhandled [ va = 0x%(2)08x%(1)08x, gfn =
0x%(4)08x%(3)08x ]
0x0040f00c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_wrmap_bf
[ gfn = 0x%(1)08x ]
-0x0040f10c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_wrmap_bf
[ gfn = 0x%(1)16x ]
+0x0040f10c CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_wrmap_bf
[ gfn = 0x%(2)08x%(1)08x ]
0x0040f00d CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_prealloc_unpin
[ gfn = 0x%(1)08x ]
-0x0040f10d CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_prealloc_unpin
[ gfn = 0x%(1)16x ]
+0x0040f10d CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_prealloc_unpin
[ gfn = 0x%(2)08x%(1)08x ]
0x0040f00e CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_full
[ gfn = 0x%(1)08x ]
-0x0040f10e CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_full
[ gfn = 0x%(1)16x ]
+0x0040f10e CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_full
[ gfn = 0x%(2)08x%(1)08x ]
0x0040f00f CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_only
[ gfn = 0x%(1)08x ]
-0x0040f10f CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_only
[ gfn = 0x%(1)16x ]
+0x0040f10f CPU%(cpu)d %(tsc)d (+%(reltsc)8d) shadow_emulate_resync_only
[ gfn = 0x%(2)08x%(1)08x ]
0x00801001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_freq_change [ %(1)dMHz ->
%(2)dMHz ]
0x00802001 CPU%(cpu)d %(tsc)d (+%(reltsc)8d) cpu_idle_entry [ C0 ->
C%(1)d, acpi_pm_tick = %(2)d, expected = %(3)dus, predicted = %(4)dus ]
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