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[Xen-changelog] [linux-2.6.18-xen] net: Intel ixgbe driver

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] [linux-2.6.18-xen] net: Intel ixgbe driver
From: "Xen patchbot-linux-2.6.18-xen" <patchbot-linux-2.6.18-xen@xxxxxxxxxxxxxxxxxxx>
Date: Fri, 30 Jan 2009 14:55:03 -0800
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# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1233312767 0
# Node ID 98897f04b338f08686eba199d6234a95cf0939f1
# Parent  b790b287bf4740ded017a4819b37813561a7c4b6
net: Intel ixgbe driver

Signed-off-by: Mitch Williams <mitch.a.williams@xxxxxxxxx>
---
 drivers/net/Kconfig                 |   26 
 drivers/net/Makefile                |    1 
 drivers/net/ixgbe/Makefile          |   39 
 drivers/net/ixgbe/ixgbe.h           |  479 +++
 drivers/net/ixgbe/ixgbe_82598.c     | 1147 +++++++
 drivers/net/ixgbe/ixgbe_api.c       |  796 +++++
 drivers/net/ixgbe/ixgbe_api.h       |  109 
 drivers/net/ixgbe/ixgbe_common.c    | 1807 +++++++++++
 drivers/net/ixgbe/ixgbe_common.h    |   77 
 drivers/net/ixgbe/ixgbe_dcb.c       |  333 ++
 drivers/net/ixgbe/ixgbe_dcb.h       |  167 +
 drivers/net/ixgbe/ixgbe_dcb_82598.c |  413 ++
 drivers/net/ixgbe/ixgbe_dcb_82598.h |   99 
 drivers/net/ixgbe/ixgbe_ethtool.c   | 1941 ++++++++++++
 drivers/net/ixgbe/ixgbe_main.c      | 5464 ++++++++++++++++++++++++++++++++++++
 drivers/net/ixgbe/ixgbe_osdep.h     |   96 
 drivers/net/ixgbe/ixgbe_param.c     |  728 ++++
 drivers/net/ixgbe/ixgbe_phy.c       |  773 +++++
 drivers/net/ixgbe/ixgbe_phy.h       |  107 
 drivers/net/ixgbe/ixgbe_type.h      | 1672 +++++++++++
 drivers/net/ixgbe/kcompat.c         |  442 ++
 drivers/net/ixgbe/kcompat.h         | 1776 +++++++++++
 22 files changed, 18488 insertions(+), 4 deletions(-)

diff -r b790b287bf47 -r 98897f04b338 drivers/net/Kconfig
--- a/drivers/net/Kconfig       Fri Jan 30 10:53:27 2009 +0900
+++ b/drivers/net/Kconfig       Fri Jan 30 10:52:47 2009 +0000
@@ -2318,12 +2318,31 @@ config CHELSIO_T1
           To compile this driver as a module, choose M here: the module
           will be called cxgb.
 
+config IXGBE
+       tristate "Intel(R) 10GbE PCI Express adapters support"
+       depends on PCI && INET
+       ---help---
+         This driver supports Intel(R) 10GbE PCI Express family of
+         adapters.  For more information on how to identify your adapter, go
+         to the Adapter & Driver ID Guide at:
+
+         <http://support.intel.com/support/network/adapter/pro100/21397.htm>
+
+         For general information and support, go to the Intel support
+         website at:
+
+         <http://support.intel.com>
+
+         To compile this driver as a module, choose M here. The module
+         will be called ixgbe.
+
 config IXGB
        tristate "Intel(R) PRO/10GbE support"
        depends on PCI
        ---help---
-         This driver supports Intel(R) PRO/10GbE family of
-         adapters.  For more information on how to identify your adapter, go
+         This driver supports Intel(R) PRO/10GbE family of adapters for
+         PCI-X type cards. For PCI-E type cards, use the "ixgbe" driver
+         instead. For more information on how to identify your adapter, go
          to the Adapter & Driver ID Guide at:
 
          <http://support.intel.com/support/network/adapter/pro100/21397.htm>
@@ -2336,8 +2355,7 @@ config IXGB
          More specific information on configuring the driver is in 
          <file:Documentation/networking/ixgb.txt>.
 
-         To compile this driver as a module, choose M here and read
-         <file:Documentation/networking/net-modules.txt>.  The module
+         To compile this driver as a module, choose M here. The module
          will be called ixgb.
 
 config IXGB_NAPI
diff -r b790b287bf47 -r 98897f04b338 drivers/net/Makefile
--- a/drivers/net/Makefile      Fri Jan 30 10:53:27 2009 +0900
+++ b/drivers/net/Makefile      Fri Jan 30 10:52:47 2009 +0000
@@ -9,6 +9,7 @@ obj-$(CONFIG_E1000) += e1000/
 obj-$(CONFIG_E1000) += e1000/
 obj-$(CONFIG_IBM_EMAC) += ibm_emac/
 obj-$(CONFIG_IXGB) += ixgb/
+obj-$(CONFIG_IXGBE) += ixgbe/
 obj-$(CONFIG_CHELSIO_T1) += chelsio/
 obj-$(CONFIG_BONDING) += bonding/
 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/Makefile
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/Makefile        Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,39 @@
+################################################################################
+#
+# Intel 10 Gigabit PCI Express Linux driver
+# Copyright(c) 1999 - 2007 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program; if not, write to the Free Software Foundation, Inc.,
+# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# The full GNU General Public License is included in this distribution in
+# the file called "COPYING".
+#
+# Contact Information:
+# Linux NICS <linux.nics@xxxxxxxxx>
+# e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+#
+################################################################################
+
+#
+# Makefile for the Intel(R) 10GbE PCI Express ethernet driver
+#
+
+obj-$(CONFIG_IXGBE) += ixgbe.o
+
+ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \
+              ixgbe_82598.o ixgbe_phy.o ixgbe_api.o ixgbe_dcb_82598.o \
+              ixgbe_dcb.o ixgbe_param.o ixgbe_phy.o kcompat.o
+EXTRA_CFLAGS += -DDRIVER_IXGBE -DCONFIG_IXGBE_RSS 
+
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe.h Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,479 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _IXGBE_H_
+#define _IXGBE_H_
+
+#ifndef IXGBE_NO_LRO
+#include <net/tcp.h>
+#endif
+
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/vmalloc.h>
+
+#ifdef SIOCETHTOOL
+#include <linux/ethtool.h>
+#endif
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#endif
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+#define IXGBE_DCA
+#include <linux/dca.h>
+
+#endif
+
+#include "ixgbe_dcb.h"
+
+#include "kcompat.h"
+
+#include "ixgbe_api.h"
+
+#define IXGBE_NO_INET_LRO
+#ifndef IXGBE_NO_LRO
+#if defined(CONFIG_INET_LRO) || defined(CONFIG_INET_LRO_MODULE)
+#include <linux/inet_lro.h>
+#define IXGBE_MAX_LRO_DESCRIPTORS                 8
+#undef IXGBE_NO_INET_LRO
+#define IXGBE_NO_LRO
+#endif
+#endif /* IXGBE_NO_LRO */
+
+#define PFX "ixgbe: "
+#define DPRINTK(nlevel, klevel, fmt, args...) \
+       ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
+       printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
+               __FUNCTION__ , ## args)))
+
+/* TX/RX descriptor defines */
+#define IXGBE_DEFAULT_TXD                 1024
+#define IXGBE_MAX_TXD                     4096
+#define IXGBE_MIN_TXD                       64
+
+#define IXGBE_DEFAULT_RXD                 1024
+#define IXGBE_MAX_RXD                     4096
+#define IXGBE_MIN_RXD                       64
+
+
+/* flow control */
+#define IXGBE_DEFAULT_FCRTL            0x10000
+#define IXGBE_MIN_FCRTL                           0x40
+#define IXGBE_MAX_FCRTL                        0x7FF80
+#define IXGBE_DEFAULT_FCRTH            0x20000
+#define IXGBE_MIN_FCRTH                          0x600
+#define IXGBE_MAX_FCRTH                        0x7FFF0
+#define IXGBE_DEFAULT_FCPAUSE           0xFFFF
+#define IXGBE_MIN_FCPAUSE                    0
+#define IXGBE_MAX_FCPAUSE               0xFFFF
+
+/* Supported Rx Buffer Sizes */
+#define IXGBE_RXBUFFER_64    64     /* Used for packet split */
+#define IXGBE_RXBUFFER_128   128    /* Used for packet split */
+#define IXGBE_RXBUFFER_256   256    /* Used for packet split */
+#define IXGBE_RXBUFFER_2048  2048
+
+#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
+
+#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
+
+#if defined(CONFIG_IXGBE_DCB) || defined(CONFIG_IXGBE_RSS) || \
+    defined(CONFIG_IXGBE_VMDQ)
+#define CONFIG_IXGBE_MQ
+#endif
+
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
+#define IXGBE_RX_BUFFER_WRITE  16      /* Must be power of 2 */
+
+#define IXGBE_TX_FLAGS_CSUM            (u32)(1)
+#define IXGBE_TX_FLAGS_VLAN            (u32)(1 << 1)
+#define IXGBE_TX_FLAGS_TSO             (u32)(1 << 2)
+#define IXGBE_TX_FLAGS_IPV4            (u32)(1 << 3)
+#define IXGBE_TX_FLAGS_VLAN_MASK       0xffff0000
+#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK  0x0000e000
+#define IXGBE_TX_FLAGS_VLAN_SHIFT      16
+
+#ifndef IXGBE_NO_LRO
+#define IXGBE_LRO_MAX 32       /*Maximum number of LRO descriptors*/
+#define IXGBE_LRO_GLOBAL 10
+
+struct ixgbe_lro_stats {
+       u32 flushed;
+       u32 coal;
+};
+
+struct ixgbe_lro_desc {
+       struct  hlist_node lro_node;
+       struct  sk_buff *skb;
+       struct  sk_buff *last_skb;
+       int     timestamp;
+       u32   tsval;
+       u32   tsecr;
+       u32   source_ip;
+       u32   dest_ip;
+       u32   next_seq;
+       u32   ack_seq;
+       u16   window;
+       u16   source_port;
+       u16   dest_port;
+       u16   append_cnt;
+       u16   mss;
+       u32   data_size;        /*TCP data size*/
+       u16   vlan_tag;
+};
+
+struct ixgbe_lro_info {
+       struct ixgbe_lro_stats stats;
+       int max;                /*Maximum number of packet to coalesce.*/
+};
+
+struct ixgbe_lro_list {
+       struct hlist_head active;
+       struct hlist_head free;
+       int active_cnt;
+};
+
+#endif /* IXGBE_NO_LRO */
+/* wrapper around a pointer to a socket buffer,
+ * so a DMA handle can be stored along with the buffer */
+struct ixgbe_tx_buffer {
+       struct sk_buff *skb;
+       dma_addr_t dma;
+       unsigned long time_stamp;
+       u16 length;
+       u16 next_to_watch;
+};
+
+struct ixgbe_rx_buffer {
+       struct sk_buff *skb;
+       dma_addr_t dma;
+       struct page *page;
+       dma_addr_t page_dma;
+       unsigned int page_offset;
+};
+
+struct ixgbe_queue_stats {
+       u64 packets;
+       u64 bytes;
+};
+
+struct ixgbe_ring {
+       void *desc;                     /* descriptor ring memory */
+       dma_addr_t dma;                 /* phys. address of descriptor ring */
+       unsigned int size;              /* length in bytes */
+       unsigned int count;             /* amount of descriptors */
+       unsigned int next_to_use;
+       unsigned int next_to_clean;
+
+       int queue_index; /* needed for multiqueue queue management */
+       union {
+               struct ixgbe_tx_buffer *tx_buffer_info;
+               struct ixgbe_rx_buffer *rx_buffer_info;
+       };
+
+       u16 head;
+       u16 tail;
+
+       unsigned int total_bytes;
+       unsigned int total_packets;
+
+       u16 reg_idx; /* holds the special value that gets the hardware register
+                     * offset associated with this ring, which is different
+                     * for DCB and RSS modes */
+
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+       /* cpu for tx queue */
+       int cpu;
+#endif
+
+       struct ixgbe_queue_stats stats;
+       u16 v_idx; /* maps directly to the index for this ring in the hardware
+                  * vector array, can also be used for finding the bit in EICR
+                  * and friends that represents the vector for this ring */
+#ifndef IXGBE_NO_LRO
+       /* LRO list for rx queue */
+       struct ixgbe_lro_list *lrolist;
+#endif
+#ifndef IXGBE_NO_INET_LRO
+       struct net_lro_mgr  lro_mgr;
+       bool lro_used;
+#endif
+       u16 work_limit;                /* max work per interrupt */
+       u16 rx_buf_len;
+};
+
+#define RING_F_DCB  0
+#define RING_F_VMDQ 1
+#define RING_F_RSS  2
+#define IXGBE_MAX_DCB_INDICES   8
+#define IXGBE_MAX_RSS_INDICES  16
+#define IXGBE_MAX_VMDQ_INDICES 16
+struct ixgbe_ring_feature {
+       int indices;
+       int mask;
+};
+
+#define MAX_RX_QUEUES 64
+#define MAX_TX_QUEUES 32
+
+#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
+                               ? 8 : 1)
+#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
+
+/* MAX_MSIX_Q_VECTORS of these are allocated,
+ * but we only use one per queue-specific vector.
+ */
+struct ixgbe_q_vector {
+       struct ixgbe_adapter *adapter;
+#ifdef CONFIG_IXGBE_NAPI
+       struct napi_struct napi;
+#endif
+       DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
+       DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
+       u8 rxr_count;     /* Rx ring count assigned to this vector */
+       u8 txr_count;     /* Tx ring count assigned to this vector */
+       u8 tx_itr;
+       u8 rx_itr;
+       u32 eitr;
+};
+
+
+/* Helper macros to switch between ints/sec and what the register uses.
+ * And yes, it's the same math going both ways.
+ */
+#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
+       ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
+#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
+
+#define IXGBE_DESC_UNUSED(R) \
+       ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
+       (R)->next_to_clean - (R)->next_to_use - 1)
+
+#define IXGBE_RX_DESC_ADV(R, i)            \
+       (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
+#define IXGBE_TX_DESC_ADV(R, i)            \
+       (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
+#define IXGBE_TX_CTXTDESC_ADV(R, i)        \
+       (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
+#define IXGBE_GET_DESC(R, i, type)     (&(((struct type *)((R).desc))[i]))
+#define IXGBE_TX_DESC(R, i)    IXGBE_GET_DESC(R, i, ixgbe_legacy_tx_desc)
+#define IXGBE_RX_DESC(R, i)    IXGBE_GET_DESC(R, i, ixgbe_legacy_rx_desc)
+
+#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
+
+#ifdef IXGBE_TCP_TIMER
+#define TCP_TIMER_VECTOR 1
+#else
+#define TCP_TIMER_VECTOR 0
+#endif
+#define OTHER_VECTOR 1
+#define NON_Q_VECTORS (OTHER_VECTOR + TCP_TIMER_VECTOR)
+
+#define MAX_MSIX_Q_VECTORS 16
+#define MIN_MSIX_Q_VECTORS 2
+#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
+#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
+
+/* board specific private data structure */
+struct ixgbe_adapter {
+       struct timer_list watchdog_timer;
+#ifdef NETIF_F_HW_VLAN_TX
+       struct vlan_group *vlgrp;
+#endif
+       u16 bd_number;
+       struct work_struct reset_task;
+       struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
+       char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
+       struct ixgbe_dcb_config dcb_cfg;
+       struct ixgbe_dcb_config temp_dcb_cfg;
+       u8 dcb_set_bitmap;
+
+       /* Interrupt Throttle Rate */
+       u32 itr_setting;
+       u16 eitr_low;
+       u16 eitr_high;
+
+       /* TX */
+       struct ixgbe_ring *tx_ring;     /* One per active queue */
+       int num_tx_queues;
+       u64 restart_queue;
+       u64 hw_csum_tx_good;
+       u64 lsc_int;
+       u64 hw_tso_ctxt;
+       u64 hw_tso6_ctxt;
+       u32 tx_timeout_count;
+       bool detect_tx_hung;
+
+       /* RX */
+       struct ixgbe_ring *rx_ring;     /* One per active queue */
+       int num_rx_queues;
+       u64 hw_csum_rx_error;
+       u64 hw_csum_rx_good;
+       u64 non_eop_descs;
+#ifndef CONFIG_IXGBE_NAPI
+       u64 rx_dropped_backlog;         /* count drops from rx intr handler */
+#endif
+       int num_msix_vectors;
+       struct ixgbe_ring_feature ring_feature[3];
+       struct msix_entry *msix_entries;
+#ifdef IXGBE_TCP_TIMER
+       irqreturn_t (*msix_handlers[MAX_MSIX_COUNT])(int irq, void *data,
+                                                    struct pt_regs *regs);
+#endif
+
+       u64 rx_hdr_split;
+       u32 alloc_rx_page_failed;
+       u32 alloc_rx_buff_failed;
+
+       /* Some features need tri-state capability,
+        * thus the additional *_CAPABLE flags.
+        */
+       u32 flags;
+#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
+#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
+#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
+#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
+#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
+#ifndef IXGBE_NO_LLI
+#define IXGBE_FLAG_LLI_PUSH                     (u32)(1 << 5)
+#endif
+#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
+#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
+#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
+#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
+#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
+#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
+#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
+#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
+#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
+#define IXGBE_FLAG_DCB_CAPABLE                  (u32)(1 << 15)
+#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
+#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
+#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
+#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
+#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
+#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
+#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1 << 23)
+
+/* default to trying for four seconds */
+#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
+
+       /* OS defined structs */
+       struct net_device *netdev;
+       struct pci_dev *pdev;
+       struct net_device_stats net_stats;
+#ifndef IXGBE_NO_LRO
+       struct ixgbe_lro_info lro_data;
+#endif
+
+#ifdef ETHTOOL_TEST
+       u32 test_icr;
+       struct ixgbe_ring test_tx_ring;
+       struct ixgbe_ring test_rx_ring;
+#endif
+
+       /* structs defined in ixgbe_hw.h */
+       struct ixgbe_hw hw;
+       u16 msg_enable;
+       struct ixgbe_hw_stats stats;
+#ifndef IXGBE_NO_LLI
+       u32 lli_port;
+       u32 lli_size;
+       u64 lli_int;
+#endif
+       /* Interrupt Throttle Rate */
+       u32 eitr_param;
+
+       unsigned long state;
+       u32 *config_space;
+       u64 tx_busy;
+#ifndef IXGBE_NO_INET_LRO
+       unsigned int lro_max_aggr;
+       unsigned int lro_aggregated;
+       unsigned int lro_flushed;
+       unsigned int lro_no_desc;
+#endif
+       unsigned int tx_ring_count;
+       unsigned int rx_ring_count;
+
+       u32 link_speed;
+       bool link_up;
+       unsigned long link_check_timeout;
+
+       struct work_struct watchdog_task;
+       struct work_struct sfp_task;
+       struct timer_list sfp_timer;
+};
+
+enum ixbge_state_t {
+       __IXGBE_TESTING,
+       __IXGBE_RESETTING,
+       __IXGBE_DOWN,
+       __IXGBE_SFP_MODULE_NOT_FOUND
+};
+
+
+/* needed by ixgbe_main.c */
+extern int ixgbe_validate_mac_addr(u8 *mc_addr);
+extern void ixgbe_check_options(struct ixgbe_adapter *adapter);
+
+/* needed by ixgbe_ethtool.c */
+extern char ixgbe_driver_name[];
+extern const char ixgbe_driver_version[];
+
+extern int ixgbe_up(struct ixgbe_adapter *adapter);
+extern void ixgbe_down(struct ixgbe_adapter *adapter);
+extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
+extern void ixgbe_reset(struct ixgbe_adapter *adapter);
+extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
+extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *,struct ixgbe_ring 
*);
+extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *,struct ixgbe_ring 
*);
+extern void ixgbe_free_rx_resources(struct ixgbe_adapter *,struct ixgbe_ring 
*);
+extern void ixgbe_free_tx_resources(struct ixgbe_adapter *,struct ixgbe_ring 
*);
+extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
+
+/* needed by ixgbe_dcb_nl.c */
+extern void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter);
+extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
+extern bool ixgbe_is_ixgbe(struct pci_dev *pcidev);
+
+#ifdef ETHTOOL_OPS_COMPAT
+extern int ethtool_ioctl(struct ifreq *ifr);
+
+#endif
+extern int ixgbe_dcb_netlink_register(void);
+extern int ixgbe_dcb_netlink_unregister(void);
+
+extern int ixgbe_sysfs_create(struct ixgbe_adapter *adapter);
+extern void ixgbe_sysfs_remove(struct ixgbe_adapter *adapter);
+
+#ifdef CONFIG_IXGBE_NAPI
+extern void ixgbe_napi_add_all(struct ixgbe_adapter *adapter);
+extern void ixgbe_napi_del_all(struct ixgbe_adapter *adapter);
+#endif
+
+#endif /* _IXGBE_H_ */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_82598.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_82598.c   Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,1147 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#include "ixgbe_type.h"
+#include "ixgbe_api.h"
+#include "ixgbe_common.h"
+#include "ixgbe_phy.h"
+
+s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
+static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg);
+s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg);
+static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
+s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
+static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
+static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
+                                      ixgbe_link_speed *speed, bool *link_up,
+                                      bool link_up_wait_to_complete);
+static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
+                                            ixgbe_link_speed speed,
+                                            bool autoneg,
+                                            bool autoneg_wait_to_complete);
+static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
+static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete);
+static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
+s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
+                         u32 vind, bool vlan_on);
+static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
+static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index);
+static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
+s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
+s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
+                                u8 *eeprom_data);
+u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
+
+/**
+ *  ixgbe_init_ops_82598 - Inits func ptrs and MAC type
+ *  @hw: pointer to hardware structure
+ *
+ *  Initialize the function pointers and assign the MAC type for 82598.
+ *  Does not touch the hardware.
+ **/
+s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
+{
+       struct ixgbe_mac_info *mac = &hw->mac;
+       struct ixgbe_phy_info *phy = &hw->phy;
+       s32 ret_val;
+       u16 list_offset, data_offset;
+
+       ret_val = ixgbe_init_phy_ops_generic(hw);
+       ret_val = ixgbe_init_ops_generic(hw);
+
+       /* MAC */
+       mac->ops.reset_hw = &ixgbe_reset_hw_82598;
+       mac->ops.get_media_type = &ixgbe_get_media_type_82598;
+       mac->ops.get_supported_physical_layer =
+                                   &ixgbe_get_supported_physical_layer_82598;
+       mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
+       mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
+
+       /* LEDs */
+       mac->ops.blink_led_start = &ixgbe_blink_led_start_82598;
+       mac->ops.blink_led_stop = &ixgbe_blink_led_stop_82598;
+
+       /* RAR, Multicast, VLAN */
+       mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
+       mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
+       mac->ops.set_vfta = &ixgbe_set_vfta_82598;
+       mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
+
+       /* Flow Control */
+       mac->ops.setup_fc = &ixgbe_setup_fc_82598;
+
+       /* Link */
+       mac->ops.check_link = &ixgbe_check_mac_link_82598;
+       if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
+               mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
+               mac->ops.setup_link_speed =
+                                    &ixgbe_setup_copper_link_speed_82598;
+               mac->ops.get_link_capabilities =
+                                    &ixgbe_get_copper_link_capabilities_82598;
+       } else {
+               mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
+               mac->ops.setup_link_speed = &ixgbe_setup_mac_link_speed_82598;
+               mac->ops.get_link_capabilities =
+                                      &ixgbe_get_link_capabilities_82598;
+       }
+
+       mac->mcft_size       = 128;
+       mac->vft_size        = 128;
+       mac->num_rar_entries = 16;
+       mac->max_tx_queues   = 32;
+       mac->max_rx_queues   = 64;
+
+       /* SFP+ Module */
+       phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
+
+       /* Call PHY identify routine to get the phy type */
+       phy->ops.identify(hw);
+
+       /* PHY Init */
+       switch (hw->phy.type) {
+       case ixgbe_phy_tn:
+               phy->ops.check_link = &ixgbe_check_phy_link_tnx;
+               phy->ops.get_firmware_version =
+                            &ixgbe_get_phy_firmware_version_tnx;
+               break;
+       case ixgbe_phy_nl:
+               phy->ops.reset = &ixgbe_reset_phy_nl;
+
+               /* Call SFP+ identify routine to get the SFP+ module type */
+               ret_val = phy->ops.identify_sfp(hw);
+               if (ret_val != 0)
+                       goto out;
+               else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
+                       ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
+                       goto out;
+               }
+
+               /* Check to see if SFP+ module is supported */
+               ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
+                                                           &list_offset,
+                                                           &data_offset);
+               if (ret_val != 0) {
+                       ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
+                       goto out;
+               }
+               break;
+       default:
+               break;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @autoneg: boolean auto-negotiation value
+ *
+ *  Determines the link capabilities by reading the AUTOC register.
+ **/
+static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg)
+{
+       s32 status = 0;
+
+       /*
+        * Determine link capabilities based on the stored value of AUTOC,
+        * which represents EEPROM defaults.
+        */
+       switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
+       case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
+               *speed = IXGBE_LINK_SPEED_1GB_FULL;
+               *autoneg = false;
+               break;
+
+       case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
+               *speed = IXGBE_LINK_SPEED_10GB_FULL;
+               *autoneg = false;
+               break;
+
+       case IXGBE_AUTOC_LMS_1G_AN:
+               *speed = IXGBE_LINK_SPEED_1GB_FULL;
+               *autoneg = true;
+               break;
+
+       case IXGBE_AUTOC_LMS_KX4_AN:
+       case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
+               *speed = IXGBE_LINK_SPEED_UNKNOWN;
+               if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
+                       *speed |= IXGBE_LINK_SPEED_10GB_FULL;
+               if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
+                       *speed |= IXGBE_LINK_SPEED_1GB_FULL;
+               *autoneg = true;
+               break;
+
+       default:
+               status = IXGBE_ERR_LINK_SETUP;
+               break;
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @autoneg: boolean auto-negotiation value
+ *
+ *  Determines the link capabilities by reading the AUTOC register.
+ **/
+s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg)
+{
+       s32 status = IXGBE_ERR_LINK_SETUP;
+       u16 speed_ability;
+
+       *speed = 0;
+       *autoneg = true;
+
+       status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
+                                     IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+                                     &speed_ability);
+
+       if (status == 0) {
+               if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
+                       *speed |= IXGBE_LINK_SPEED_10GB_FULL;
+               if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
+                       *speed |= IXGBE_LINK_SPEED_1GB_FULL;
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_get_media_type_82598 - Determines media type
+ *  @hw: pointer to hardware structure
+ *
+ *  Returns the media type (fiber, copper, backplane)
+ **/
+static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
+{
+       enum ixgbe_media_type media_type;
+
+       /* Media type for I82598 is based on device ID */
+       switch (hw->device_id) {
+       case IXGBE_DEV_ID_82598:
+               /* Default device ID is mezzanine card KX/KX4 */
+               media_type = ixgbe_media_type_backplane;
+               break;
+       case IXGBE_DEV_ID_82598AF_DUAL_PORT:
+       case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
+       case IXGBE_DEV_ID_82598EB_CX4:
+       case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
+       case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
+       case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
+       case IXGBE_DEV_ID_82598EB_XF_LR:
+       case IXGBE_DEV_ID_82598EB_SFP_LOM:
+               media_type = ixgbe_media_type_fiber;
+               break;
+       case IXGBE_DEV_ID_82598AT:
+               media_type = ixgbe_media_type_copper;
+               break;
+       default:
+               media_type = ixgbe_media_type_unknown;
+               break;
+       }
+
+       return media_type;
+}
+
+/**
+ *  ixgbe_fc_enable_82598 - Enable flow control
+ *  @hw: pointer to hardware structure
+ *  @packetbuf_num: packet buffer number (0-7)
+ *
+ *  Enable flow control according to the current settings.
+ **/
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+{
+       s32 ret_val = 0;
+       u32 fctrl_reg;
+       u32 rmcs_reg;
+       u32 reg;
+
+       fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+       fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
+
+       rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
+       rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
+
+       /*
+        * The possible values of fc.current_mode are:
+        * 0: Flow control is completely disabled
+        * 1: Rx flow control is enabled (we can receive pause frames,
+        *    but not send pause frames).
+        * 2:  Tx flow control is enabled (we can send pause frames but
+        *     we do not support receiving pause frames).
+        * 3: Both Rx and Tx flow control (symmetric) are enabled.
+        * other: Invalid.
+        */
+       switch (hw->fc.current_mode) {
+       case ixgbe_fc_none:
+               /* Flow control completely disabled by software override. */
+               break;
+       case ixgbe_fc_rx_pause:
+               /*
+                * Rx Flow control is enabled and Tx Flow control is
+                * disabled by software override. Since there really
+                * isn't a way to advertise that we are capable of RX
+                * Pause ONLY, we will advertise that we support both
+                * symmetric and asymmetric Rx PAUSE.  Later, we will
+                * disable the adapter's ability to send PAUSE frames.
+                */
+               fctrl_reg |= IXGBE_FCTRL_RFCE;
+               break;
+       case ixgbe_fc_tx_pause:
+               /*
+                * Tx Flow control is enabled, and Rx Flow control is
+                * disabled by software override.
+                */
+               rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
+               break;
+       case ixgbe_fc_full:
+               /* Flow control (both Rx and Tx) is enabled by SW override. */
+               fctrl_reg |= IXGBE_FCTRL_RFCE;
+               rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
+               break;
+       default:
+               hw_dbg(hw, "Flow control param set incorrectly\n");
+               ret_val = -IXGBE_ERR_CONFIG;
+               goto out;
+               break;
+       }
+
+       /* Enable 802.3x based flow control settings. */
+       IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
+       IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
+
+       /* Set up and enable Rx high/low water mark thresholds, enable XON. */
+       if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
+               if (hw->fc.send_xon) {
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
+                                       (hw->fc.low_water | IXGBE_FCRTL_XONE));
+               } else {
+                       IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
+                                       hw->fc.low_water);
+               }
+
+               IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
+                               (hw->fc.high_water | IXGBE_FCRTH_FCEN));
+       }
+
+       /* Configure pause time (2 TCs per register) */
+       reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
+       if ((packetbuf_num & 1) == 0)
+               reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
+       else
+               reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
+       IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
+
+       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
+
+out:
+       return ret_val;
+}
+
+/**
+ *  ixgbe_setup_fc_82598 - Set up flow control
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets up flow control.
+ **/
+s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+{
+       s32 ret_val = 0;
+
+       /* Validate the packetbuf configuration */
+       if (packetbuf_num < 0 || packetbuf_num > 7) {
+               hw_dbg(hw, "Invalid packet buffer number [%d], expected range 
is"
+                         " 0-7\n", packetbuf_num);
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+               goto out;
+       }
+
+       /*
+        * Validate the water mark configuration.  Zero water marks are invalid
+        * because it causes the controller to just blast out fc packets.
+        */
+       if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
+               hw_dbg(hw, "Invalid water mark configuration\n");
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+               goto out;
+       }
+
+       /*
+        * Validate the requested mode.  Strict IEEE mode does not allow
+        * ixgbe_fc_rx_pause because it will cause testing anomalies.
+        */
+       if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
+               hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
+               ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
+               goto out;
+       }
+
+       /*
+        * 10gig parts do not have a word in the EEPROM to determine the
+        * default flow control setting, so we explicitly set it to full.
+        */
+       if (hw->fc.requested_mode == ixgbe_fc_default)
+               hw->fc.requested_mode = ixgbe_fc_full;
+
+       /*
+        * Save off the requested flow control mode for use later.  Depending
+        * on the link partner's capabilities, we may or may not use this mode.
+        */
+       hw->fc.current_mode = hw->fc.requested_mode;
+
+
+       ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
+
+out:
+       return ret_val;
+}
+
+/**
+ *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
+ *  @hw: pointer to hardware structure
+ *
+ *  Configures link settings based on values in the ixgbe_hw struct.
+ *  Restarts the link.  Performs autonegotiation if needed.
+ **/
+static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
+{
+       u32 autoc_reg;
+       u32 links_reg;
+       u32 i;
+       s32 status = 0;
+
+       /* Restart link */
+       autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       autoc_reg |= IXGBE_AUTOC_AN_RESTART;
+       IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+
+       /* Only poll for autoneg to complete if specified to do so */
+       if (hw->phy.autoneg_wait_to_complete) {
+               if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
+                    IXGBE_AUTOC_LMS_KX4_AN ||
+                   (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
+                    IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
+                       links_reg = 0; /* Just in case Autoneg time = 0 */
+                       for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
+                               links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
+                               if (links_reg & IXGBE_LINKS_KX_AN_COMP)
+                                       break;
+                               msleep(100);
+                       }
+                       if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
+                               status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
+                               hw_dbg(hw, "Autonegotiation did not 
complete.\n");
+                       }
+               }
+       }
+
+       /* Set up flow control */
+       status = ixgbe_setup_fc_82598(hw, 0);
+
+       /* Add delay to filter out noises during initial link setup */
+       msleep(50);
+
+       return status;
+}
+
+/**
+ *  ixgbe_check_mac_link_82598 - Get link/speed status
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @link_up: true is link is up, false otherwise
+ *  @link_up_wait_to_complete: bool used to wait for link up or not
+ *
+ *  Reads the links register to determine if link is up and the current speed
+ **/
+static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
+                                      ixgbe_link_speed *speed, bool *link_up,
+                                      bool link_up_wait_to_complete)
+{
+       u32 links_reg;
+       u32 i;
+       u16 link_reg, adapt_comp_reg;
+
+       /*
+        * SERDES PHY requires us to read link status from undocumented
+        * register 0xC79F.  Bit 0 set indicates link is up/ready; clear
+        * indicates link down.  OxC00C is read to check that the XAUI lanes
+        * are active.  Bit 0 clear indicates active; set indicates inactive.
+        */
+       if (hw->phy.type == ixgbe_phy_nl) {
+               hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
+               hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
+               hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
+                                    &adapt_comp_reg);
+               if (link_up_wait_to_complete) {
+                       for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
+                               if ((link_reg & 1) &&
+                                   ((adapt_comp_reg & 1) == 0)) {
+                                       *link_up = true;
+                                       break;
+                               } else {
+                                       *link_up = false;
+                               }
+                               msleep(100);
+                               hw->phy.ops.read_reg(hw, 0xC79F,
+                                                    IXGBE_TWINAX_DEV,
+                                                    &link_reg);
+                               hw->phy.ops.read_reg(hw, 0xC00C,
+                                                    IXGBE_TWINAX_DEV,
+                                                    &adapt_comp_reg);
+                       }
+               } else {
+                       if ((link_reg & 1) &&
+                           ((adapt_comp_reg & 1) == 0))
+                               *link_up = true;
+                       else
+                               *link_up = false;
+               }
+
+               if (*link_up == false)
+                       goto out;
+       }
+
+       links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
+       if (link_up_wait_to_complete) {
+               for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
+                       if (links_reg & IXGBE_LINKS_UP) {
+                               *link_up = true;
+                               break;
+                       } else {
+                               *link_up = false;
+                       }
+                       msleep(100);
+                       links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
+               }
+       } else {
+               if (links_reg & IXGBE_LINKS_UP)
+                       *link_up = true;
+               else
+                       *link_up = false;
+       }
+
+       if (links_reg & IXGBE_LINKS_SPEED)
+               *speed = IXGBE_LINK_SPEED_10GB_FULL;
+       else
+               *speed = IXGBE_LINK_SPEED_1GB_FULL;
+
+out:
+       return 0;
+}
+
+/**
+ *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: true if autonegotiation enabled
+ *  @autoneg_wait_to_complete: true when waiting for completion is needed
+ *
+ *  Set the link speed in the AUTOC register and restarts link.
+ **/
+static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
+                                           ixgbe_link_speed speed, bool 
autoneg,
+                                           bool autoneg_wait_to_complete)
+{
+       s32              status            = 0;
+       ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
+       u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       u32              autoc             = curr_autoc;
+       u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
+
+       /* Check to see if speed passed in is supported. */
+       ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
+       speed &= link_capabilities;
+
+       if (speed == IXGBE_LINK_SPEED_UNKNOWN)
+               status = IXGBE_ERR_LINK_SETUP;
+
+       /* Set KX4/KX support according to speed requested */
+       else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
+                link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
+               autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
+               if (speed & IXGBE_LINK_SPEED_10GB_FULL)
+                       autoc |= IXGBE_AUTOC_KX4_SUPP;
+               if (speed & IXGBE_LINK_SPEED_1GB_FULL)
+                       autoc |= IXGBE_AUTOC_KX_SUPP;
+               if (autoc != curr_autoc)
+                       IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
+       }
+
+       if (status == 0) {
+               hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
+
+               /*
+                * Setup and restart the link based on the new values in
+                * ixgbe_hw This will write the AUTOC register based on the new
+                * stored values
+                */
+               status = ixgbe_setup_mac_link_82598(hw);
+       }
+
+       return status;
+}
+
+
+/**
+ *  ixgbe_setup_copper_link_82598 - Setup copper link settings
+ *  @hw: pointer to hardware structure
+ *
+ *  Configures link settings based on values in the ixgbe_hw struct.
+ *  Restarts the link.  Performs autonegotiation if needed.  Restart
+ *  phy and wait for autonegotiate to finish.  Then synchronize the
+ *  MAC and PHY.
+ **/
+static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
+{
+       s32 status;
+       u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       u32 autoc = curr_autoc;
+
+       /* Restart autonegotiation on PHY */
+       status = hw->phy.ops.setup_link(hw);
+
+       /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
+       autoc &= ~IXGBE_AUTOC_LMS_MASK;
+       autoc |= IXGBE_AUTOC_LMS_KX4_AN;
+
+       autoc &= ~(IXGBE_AUTOC_1G_PMA_PMD_MASK | IXGBE_AUTOC_10G_PMA_PMD_MASK);
+       autoc |= (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
+
+       if (autoc != curr_autoc)
+               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
+
+       /* Set up MAC */
+       ixgbe_setup_mac_link_82598(hw);
+
+       return status;
+}
+
+/**
+ *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: true if autonegotiation enabled
+ *  @autoneg_wait_to_complete: true if waiting is needed to complete
+ *
+ *  Sets the link speed in the AUTOC register in the MAC and restarts link.
+ **/
+static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete)
+{
+       s32 status;
+       u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       u32 autoc = curr_autoc;
+
+       /* Setup the PHY according to input speed */
+       status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
+                                             autoneg_wait_to_complete);
+
+       /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
+       autoc &= ~IXGBE_AUTOC_LMS_MASK;
+       autoc |= IXGBE_AUTOC_LMS_KX4_AN;
+
+       autoc &= ~(IXGBE_AUTOC_1G_PMA_PMD_MASK | IXGBE_AUTOC_10G_PMA_PMD_MASK);
+       autoc |= (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
+
+       if (autoc != curr_autoc)
+               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
+
+       /* Set up MAC */
+       ixgbe_setup_mac_link_82598(hw);
+
+       return status;
+}
+
+/**
+ *  ixgbe_reset_hw_82598 - Performs hardware reset
+ *  @hw: pointer to hardware structure
+ *
+ *  Resets the hardware by resetting the transmit and receive units, masks and
+ *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
+ *  reset.
+ **/
+static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
+{
+       s32 status = 0;
+       u32 ctrl;
+       u32 gheccr;
+       u32 i;
+       u32 autoc;
+       u8  analog_val;
+
+       /* Call adapter stop to disable tx/rx and clear interrupts */
+       hw->mac.ops.stop_adapter(hw);
+
+       /*
+        * Power up the Atlas Tx lanes if they are currently powered down.
+        * Atlas Tx lanes are powered down for MAC loopback tests, but
+        * they are not automatically restored on reset.
+        */
+       hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
+       if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
+               /* Enable Tx Atlas so packets can be transmitted again */
+               hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
+                                            &analog_val);
+               analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
+               hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
+                                             analog_val);
+
+               hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
+                                            &analog_val);
+               analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
+               hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
+                                             analog_val);
+
+               hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
+                                            &analog_val);
+               analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
+               hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
+                                             analog_val);
+
+               hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
+                                            &analog_val);
+               analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
+               hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
+                                             analog_val);
+       }
+
+       /* Reset PHY */
+       if (hw->phy.reset_disable == false)
+               hw->phy.ops.reset(hw);
+
+       /*
+        * Prevent the PCI-E bus from from hanging by disabling PCI-E master
+        * access and verify no pending requests before reset
+        */
+       if (ixgbe_disable_pcie_master(hw) != 0) {
+               status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
+               hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+       }
+
+       /*
+        * Issue global reset to the MAC.  This needs to be a SW reset.
+        * If link reset is used, it might reset the MAC when mng is using it
+        */
+       ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
+       IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
+       IXGBE_WRITE_FLUSH(hw);
+
+       /* Poll for reset bit to self-clear indicating reset is complete */
+       for (i = 0; i < 10; i++) {
+               udelay(1);
+               ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
+               if (!(ctrl & IXGBE_CTRL_RST))
+                       break;
+       }
+       if (ctrl & IXGBE_CTRL_RST) {
+               status = IXGBE_ERR_RESET_FAILED;
+               hw_dbg(hw, "Reset polling failed to complete.\n");
+       }
+
+       msleep(50);
+
+       gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
+       gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
+       IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
+
+       /*
+        * Store the original AUTOC value if it has not been
+        * stored off yet.  Otherwise restore the stored original
+        * AUTOC value since the reset operation sets back to deaults.
+        */
+       autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       if (hw->mac.orig_link_settings_stored == false) {
+               hw->mac.orig_autoc = autoc;
+               hw->mac.orig_link_settings_stored = true;
+       }
+    else if (autoc != hw->mac.orig_autoc) {
+               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
+       }
+
+       /* Store the permanent mac address */
+       hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
+       return status;
+}
+
+/**
+ *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to associate with a VMDq index
+ *  @vmdq: VMDq set index
+ **/
+s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+{
+       u32 rar_high;
+
+       rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
+       rar_high &= ~IXGBE_RAH_VIND_MASK;
+       rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
+       IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
+       return 0;
+}
+
+/**
+ *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to associate with a VMDq index
+ *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
+ **/
+static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+{
+       u32 rar_high;
+       u32 rar_entries = hw->mac.num_rar_entries;
+
+
+       if (rar < rar_entries) {
+               rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
+               if (rar_high & IXGBE_RAH_VIND_MASK) {
+                       rar_high &= ~IXGBE_RAH_VIND_MASK;
+                       IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
+               }
+       } else {
+               hw_dbg(hw, "RAR index %d is out of range.\n", rar);
+       }
+
+       return 0;
+}
+
+/**
+ *  ixgbe_set_vfta_82598 - Set VLAN filter table
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
+ *  @vind: VMDq output index that maps queue to VLAN id in VFTA
+ *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
+ *
+ *  Turn on/off specified VLAN in the VLAN filter table.
+ **/
+s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+                                                     bool vlan_on)
+{
+       u32 regindex;
+       u32 bitindex;
+       u32 bits;
+       u32 vftabyte;
+
+       if (vlan > 4095)
+               return IXGBE_ERR_PARAM;
+
+       /* Determine 32-bit word position in array */
+       regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
+
+       /* Determine the location of the (VMD) queue index */
+       vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
+       bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
+
+       /* Set the nibble for VMD queue index */
+       bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
+       bits &= (~(0x0F << bitindex));
+       bits |= (vind << bitindex);
+       IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
+
+       /* Determine the location of the bit for this VLAN id */
+       bitindex = vlan & 0x1F;   /* lower five bits */
+
+       bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
+       if (vlan_on)
+               /* Turn on this VLAN id */
+               bits |= (1 << bitindex);
+       else
+               /* Turn off this VLAN id */
+               bits &= ~(1 << bitindex);
+       IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ **/
+static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
+{
+       u32 offset;
+       u32 vlanbyte;
+
+       for (offset = 0; offset < hw->mac.vft_size; offset++)
+               IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
+
+       for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
+               for (offset = 0; offset < hw->mac.vft_size; offset++)
+                       IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
+                                       0);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_blink_led_start_82598 - Blink LED based on index.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to blink
+ **/
+static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
+{
+       ixgbe_link_speed speed = 0;
+       bool link_up = 0;
+       u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+
+       /*
+        * Link must be up to auto-blink the LEDs on the 82598EB MAC;
+        * force it if link is down.
+        */
+       hw->mac.ops.check_link(hw, &speed, &link_up, false);
+
+       if (!link_up) {
+               autoc_reg |= IXGBE_AUTOC_FLU;
+               IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+               msleep(10);
+       }
+
+       led_reg &= ~IXGBE_LED_MODE_MASK(index);
+       led_reg |= IXGBE_LED_BLINK(index);
+       IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
+       IXGBE_WRITE_FLUSH(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to stop blinking
+ **/
+static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
+{
+       u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+
+       autoc_reg &= ~IXGBE_AUTOC_FLU;
+       autoc_reg |= IXGBE_AUTOC_AN_RESTART;
+       IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
+
+       led_reg &= ~IXGBE_LED_MODE_MASK(index);
+       led_reg &= ~IXGBE_LED_BLINK(index);
+       led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
+       IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
+       IXGBE_WRITE_FLUSH(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to read
+ *  @val: read value
+ *
+ *  Performs read operation to Atlas analog register specified.
+ **/
+s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
+{
+       u32  atlas_ctl;
+
+       IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
+                       IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(10);
+       atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
+       *val = (u8)atlas_ctl;
+
+       return 0;
+}
+
+/**
+ *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: atlas register to write
+ *  @val: value to write
+ *
+ *  Performs write operation to Atlas analog register specified.
+ **/
+s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
+{
+       u32  atlas_ctl;
+
+       atlas_ctl = (reg << 8) | val;
+       IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(10);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to read
+ *  @eeprom_data: value read
+ *
+ *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
+                                u8 *eeprom_data)
+{
+       s32 status = 0;
+       u16 sfp_addr = 0;
+       u16 sfp_data = 0;
+       u16 sfp_stat = 0;
+       u32 i;
+
+       if (hw->phy.type == ixgbe_phy_nl) {
+               /*
+                * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
+                * 0xC30D. These registers are used to talk to the SFP+
+                * module's EEPROM through the SDA/SCL (I2C) interface.
+                */
+               sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
+               sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
+               hw->phy.ops.write_reg(hw,
+                                     IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
+                                     IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+                                     sfp_addr);
+
+               /* Poll status */
+               for (i = 0; i < 100; i++) {
+                       hw->phy.ops.read_reg(hw,
+                                            IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
+                                            IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+                                            &sfp_stat);
+                       sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
+                       if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
+                               break;
+                       msleep(10);
+               }
+
+               if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
+                       hw_dbg(hw, "EEPROM read did not pass.\n");
+                       status = IXGBE_ERR_SFP_NOT_PRESENT;
+                       goto out;
+               }
+
+               /* Read data */
+               hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
+                                    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
+
+               *eeprom_data = (u8)(sfp_data >> 8);
+       } else {
+               status = IXGBE_ERR_PHY;
+               goto out;
+       }
+
+out:
+       return status;
+}
+
+/**
+ *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
+{
+       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+
+       switch (hw->device_id) {
+       case IXGBE_DEV_ID_82598:
+               /* Default device ID is mezzanine card KX/KX4 */
+               physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
+                                 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
+               break;
+       case IXGBE_DEV_ID_82598EB_CX4:
+       case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
+               physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
+               break;
+       case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
+               physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
+               break;
+       case IXGBE_DEV_ID_82598AF_DUAL_PORT:
+       case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
+       case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
+               physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
+               break;
+       case IXGBE_DEV_ID_82598EB_XF_LR:
+               physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
+               break;
+       case IXGBE_DEV_ID_82598AT:
+               physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
+                                 IXGBE_PHYSICAL_LAYER_1000BASE_T);
+               break;
+       case IXGBE_DEV_ID_82598EB_SFP_LOM:
+               hw->phy.ops.identify_sfp(hw);
+
+               switch (hw->phy.sfp_type) {
+               case ixgbe_sfp_type_da_cu:
+                       physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
+                       break;
+               case ixgbe_sfp_type_sr:
+                       physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
+                       break;
+               case ixgbe_sfp_type_lr:
+                       physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
+                       break;
+               default:
+                       physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+                       break;
+               }
+               break;
+
+       default:
+               physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+               break;
+       }
+
+       return physical_layer;
+}
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_api.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_api.c     Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,796 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#include "ixgbe_api.h"
+#include "ixgbe_common.h"
+
+extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
+
+/**
+ *  ixgbe_init_shared_code - Initialize the shared code
+ *  @hw: pointer to hardware structure
+ *
+ *  This will assign function pointers and assign the MAC type and PHY code.
+ *  Does not touch the hardware. This function must be called prior to any
+ *  other function in the shared code. The ixgbe_hw structure should be
+ *  memset to 0 prior to calling this function.  The following fields in
+ *  hw structure should be filled in prior to calling this function:
+ *  hw_addr, back, device_id, vendor_id, subsystem_device_id,
+ *  subsystem_vendor_id, and revision_id
+ **/
+s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
+{
+       s32 status;
+
+       /*
+        * Set the mac type
+        */
+       ixgbe_set_mac_type(hw);
+
+       switch (hw->mac.type) {
+       case ixgbe_mac_82598EB:
+               status = ixgbe_init_ops_82598(hw);
+               break;
+       default:
+               status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
+               break;
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_set_mac_type - Sets MAC type
+ *  @hw: pointer to the HW structure
+ *
+ *  This function sets the mac type of the adapter based on the
+ *  vendor ID and device ID stored in the hw structure.
+ **/
+s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
+{
+       s32 ret_val = 0;
+
+       if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
+               switch (hw->device_id) {
+               case IXGBE_DEV_ID_82598:
+               case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
+               case IXGBE_DEV_ID_82598AF_DUAL_PORT:
+               case IXGBE_DEV_ID_82598AT:
+               case IXGBE_DEV_ID_82598EB_CX4:
+               case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
+               case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
+               case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
+               case IXGBE_DEV_ID_82598EB_XF_LR:
+               case IXGBE_DEV_ID_82598EB_SFP_LOM:
+                       hw->mac.type = ixgbe_mac_82598EB;
+                       break;
+               default:
+                       ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
+                       break;
+               }
+       } else {
+               ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
+       }
+
+       hw_dbg(hw, "ixgbe_set_mac_type found mac: %d, returns: %d\n",
+                 hw->mac.type, ret_val);
+       return ret_val;
+}
+
+/**
+ *  ixgbe_init_hw - Initialize the hardware
+ *  @hw: pointer to hardware structure
+ *
+ *  Initialize the hardware by resetting and then starting the hardware
+ **/
+s32 ixgbe_init_hw(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_reset_hw - Performs a hardware reset
+ *  @hw: pointer to hardware structure
+ *
+ *  Resets the hardware by resetting the transmit and receive units, masks and
+ *  clears all interrupts, performs a PHY reset, and performs a MAC reset
+ **/
+s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_start_hw - Prepares hardware for Rx/Tx
+ *  @hw: pointer to hardware structure
+ *
+ *  Starts the hardware by filling the bus info structure and media type,
+ *  clears all on chip counters, initializes receive address registers,
+ *  multicast table, VLAN filter table, calls routine to setup link and
+ *  flow control settings, and leaves transmit and receive units disabled
+ *  and uninitialized.
+ **/
+s32 ixgbe_start_hw(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_clear_hw_cntrs - Clear hardware counters
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears all hardware statistics counters by reading them from the hardware
+ *  Statistics counters are clear on read.
+ **/
+s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_media_type - Get media type
+ *  @hw: pointer to hardware structure
+ *
+ *  Returns the media type (fiber, copper, backplane)
+ **/
+enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
+                              ixgbe_media_type_unknown);
+}
+
+/**
+ *  ixgbe_get_mac_addr - Get MAC address
+ *  @hw: pointer to hardware structure
+ *  @mac_addr: Adapter MAC address
+ *
+ *  Reads the adapter's MAC address from the first Receive Address Register
+ *  (RAR0) A reset of the adapter must have been performed prior to calling
+ *  this function in order for the MAC address to have been loaded from the
+ *  EEPROM into RAR0
+ **/
+s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
+                              (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_bus_info - Set PCI bus info
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
+ **/
+s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_num_of_tx_queues - Get Tx queues
+ *  @hw: pointer to hardware structure
+ *
+ *  Returns the number of transmit queues for the given adapter.
+ **/
+u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
+{
+       return hw->mac.max_tx_queues;
+}
+
+/**
+ *  ixgbe_get_num_of_rx_queues - Get Rx queues
+ *  @hw: pointer to hardware structure
+ *
+ *  Returns the number of receive queues for the given adapter.
+ **/
+u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
+{
+       return hw->mac.max_rx_queues;
+}
+
+/**
+ *  ixgbe_stop_adapter - Disable Rx/Tx units
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
+ *  disables transmit and receive units. The adapter_stopped flag is used by
+ *  the shared code and drivers to determine if the adapter is in a stopped
+ *  state and should not touch the hardware.
+ **/
+s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_read_pba_num - Reads part number from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number from the EEPROM
+ *
+ *  Reads the part number from the EEPROM.
+ **/
+s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
+{
+       return ixgbe_read_pba_num_generic(hw, pba_num);
+}
+
+/**
+ *  ixgbe_identify_phy - Get PHY type
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines the physical layer module found on the current adapter.
+ **/
+s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
+{
+       s32 status = 0;
+
+       if (hw->phy.type == ixgbe_phy_unknown) {
+               status = ixgbe_call_func(hw,
+                                        hw->phy.ops.identify,
+                                        (hw),
+                                        IXGBE_NOT_IMPLEMENTED);
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_reset_phy - Perform a PHY reset
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
+{
+       s32 status = 0;
+
+       if (hw->phy.type == ixgbe_phy_unknown) {
+               if (ixgbe_identify_phy(hw) != 0)
+                       status = IXGBE_ERR_PHY;
+       }
+
+       if (status == 0) {
+               status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
+                                        IXGBE_NOT_IMPLEMENTED);
+       }
+       return status;
+}
+
+/**
+ *  ixgbe_get_phy_firmware_version -
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to firmware version
+ **/
+s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
+{
+       s32 status = 0;
+
+       status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
+                                (hw, firmware_version),
+                                IXGBE_NOT_IMPLEMENTED);
+       return status;
+}
+
+/**
+ *  ixgbe_read_phy_reg - Read PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @phy_data: Pointer to read data from PHY register
+ *
+ *  Reads a value from a specified PHY register
+ **/
+s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                       u16 *phy_data)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
+                              device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_write_phy_reg - Write PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @phy_data: Data to write to the PHY register
+ *
+ *  Writes a value to specified PHY register
+ **/
+s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                        u16 phy_data)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
+                              device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_setup_phy_link - Restart PHY autoneg
+ *  @hw: pointer to hardware structure
+ *
+ *  Restart autonegotiation and PHY and waits for completion.
+ **/
+s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_check_phy_link - Determine link and speed status
+ *  @hw: pointer to hardware structure
+ *
+ *  Reads a PHY register to determine if link is up and the current speed for
+ *  the PHY.
+ **/
+s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                         bool *link_up)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
+                              link_up), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_setup_phy_link_speed - Set auto advertise
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: true if autonegotiation enabled
+ *
+ *  Sets the auto advertised capabilities
+ **/
+s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+                               bool autoneg,
+                               bool autoneg_wait_to_complete)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
+                              autoneg, autoneg_wait_to_complete),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_setup_link - Configure link settings
+ *  @hw: pointer to hardware structure
+ *
+ *  Configures link settings based on values in the ixgbe_hw struct.
+ *  Restarts the link.  Performs autonegotiation if needed.
+ **/
+s32 ixgbe_setup_link(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_check_link - Get link and speed status
+ *  @hw: pointer to hardware structure
+ *
+ *  Reads the links register to determine if link is up and the current speed
+ **/
+s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                     bool *link_up, bool link_up_wait_to_complete)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
+                              link_up, link_up_wait_to_complete),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_setup_link_speed - Set link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: true if autonegotiation enabled
+ *
+ *  Set the link speed and restarts the link.
+ **/
+s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+                           bool autoneg,
+                           bool autoneg_wait_to_complete)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.setup_link_speed, (hw, speed,
+                              autoneg, autoneg_wait_to_complete),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_link_capabilities - Returns link capabilities
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines the link capabilities of the current configuration.
+ **/
+s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                                bool *autoneg)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
+                              speed, autoneg), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_led_on - Turn on LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn on
+ *
+ *  Turns on the software controllable LEDs.
+ **/
+s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_led_off - Turn off LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn off
+ *
+ *  Turns off the software controllable LEDs.
+ **/
+s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_blink_led_start - Blink LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to blink
+ *
+ *  Blink LED based on index.
+ **/
+s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_blink_led_stop - Stop blinking LEDs
+ *  @hw: pointer to hardware structure
+ *
+ *  Stop blinking LED based on index.
+ **/
+s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_init_eeprom_params - Initialize EEPROM parameters
+ *  @hw: pointer to hardware structure
+ *
+ *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
+ *  ixgbe_hw struct in order to set up EEPROM access.
+ **/
+s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+
+/**
+ *  ixgbe_write_eeprom - Write word to EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @data: 16 bit word to be written to the EEPROM
+ *
+ *  Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
+ *  called after this function, the EEPROM will most likely contain an
+ *  invalid checksum.
+ **/
+s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
+{
+       return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_read_eeprom - Read word from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be read
+ *  @data: read 16 bit value from EEPROM
+ *
+ *  Reads 16 bit value from EEPROM
+ **/
+s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
+{
+       return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
+ *  @hw: pointer to hardware structure
+ *  @checksum_val: calculated checksum
+ *
+ *  Performs checksum calculation and validates the EEPROM checksum
+ **/
+s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
+{
+       return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
+                              (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_set_rar - Set Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq "set"
+ *  @enable_addr: set flag that address is active
+ *
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                  u32 enable_addr)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
+                              enable_addr), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_clear_rar - Clear Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_set_vmdq - Associate a VMDq index with a receive address
+ *  @hw: pointer to hardware structure
+ *  @rar: receive address register index to associate with VMDq index
+ *  @vmdq: VMDq set or pool index
+ **/
+s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
+ *  @hw: pointer to hardware structure
+ *  @rar: receive address register index to disassociate with VMDq index
+ *  @vmdq: VMDq set or pool index
+ **/
+s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_init_rx_addrs - Initializes receive address filters.
+ *  @hw: pointer to hardware structure
+ *
+ *  Places the MAC address in receive address register 0 and clears the rest
+ *  of the receive address registers. Clears the multicast table. Assumes
+ *  the receiver is in reset when the routine is called.
+ **/
+s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
+ *  @hw: pointer to hardware structure
+ **/
+u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
+{
+       return hw->mac.num_rar_entries;
+}
+
+/**
+ *  ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
+ *  @hw: pointer to hardware structure
+ *  @addr_list: the list of new multicast addresses
+ *  @addr_count: number of addresses
+ *  @func: iterator function to walk the multicast address list
+ *
+ *  The given list replaces any existing list. Clears the secondary addrs from
+ *  receive address registers. Uses unused receive address registers for the
+ *  first secondary addresses, and falls back to promiscuous mode as needed.
+ **/
+s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
+                              u32 addr_count, ixgbe_mc_addr_itr func)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
+                              addr_list, addr_count, func),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
+ *  @hw: pointer to hardware structure
+ *  @mc_addr_list: the list of new multicast addresses
+ *  @mc_addr_count: number of addresses
+ *  @func: iterator function to walk the multicast address list
+ *
+ *  The given list replaces any existing list. Clears the MC addrs from receive
+ *  address registers and the multicast table. Uses unused receive address
+ *  registers for the first multicast addresses, and hashes the rest into the
+ *  multicast table.
+ **/
+s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                              u32 mc_addr_count, ixgbe_mc_addr_itr func)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
+                              mc_addr_list, mc_addr_count, func),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_enable_mc - Enable multicast address in RAR
+ *  @hw: pointer to hardware structure
+ *
+ *  Enables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_disable_mc - Disable multicast address in RAR
+ *  @hw: pointer to hardware structure
+ *
+ *  Disables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_clear_vfta - Clear VLAN filter table
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ **/
+s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_set_vfta - Set VLAN filter table
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
+ *  @vind: VMDq output index that maps queue to VLAN id in VFTA
+ *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
+ *
+ *  Turn on/off specified VLAN in the VLAN filter table.
+ **/
+s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
+                              vlan_on), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_setup_fc - Set flow control
+ *  @hw: pointer to hardware structure
+ *  @packetbuf_num: packet buffer number (0-7)
+ *
+ *  Configures the flow control settings based on SW configuration.
+ **/
+s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw, packetbuf_num),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_read_analog_reg8 - Reads 8 bit analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to read
+ *  @val: read value
+ *
+ *  Performs write operation to analog register specified.
+ **/
+s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
+                              val), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_write_analog_reg8 - Writes 8 bit analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to write
+ *  @val: value to write
+ *
+ *  Performs write operation to Atlas analog register specified.
+ **/
+s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
+                              val), IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
+ *  @hw: pointer to hardware structure
+ *
+ *  Initializes the Unicast Table Arrays to zero on device load.  This
+ *  is part of the Rx init addr execution path.
+ **/
+s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
+                              IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to read
+ *  @eeprom_data: value read
+ *
+ *  Performs byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
+{
+       return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
+                             (hw, byte_offset, eeprom_data),
+                             IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_get_supported_physical_layer - Returns physical layer type
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
+                              (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
+}
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_api.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_api.h     Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,109 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _IXGBE_API_H_
+#define _IXGBE_API_H_
+
+#include "ixgbe_type.h"
+
+s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
+
+s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
+s32 ixgbe_init_hw(struct ixgbe_hw *hw);
+s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
+s32 ixgbe_start_hw(struct ixgbe_hw *hw);
+s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
+enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
+s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
+s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
+u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
+u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
+s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
+s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
+
+s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
+s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
+s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                       u16 *phy_data);
+s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                        u16 phy_data);
+
+s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
+s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
+                         ixgbe_link_speed *speed,
+                         bool *link_up);
+s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
+                               ixgbe_link_speed speed,
+                               bool autoneg,
+                               bool autoneg_wait_to_complete);
+s32 ixgbe_setup_link(struct ixgbe_hw *hw);
+s32 ixgbe_setup_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+                           bool autoneg, bool autoneg_wait_to_complete);
+s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                     bool *link_up, bool link_up_wait_to_complete);
+s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                            bool *autoneg);
+s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
+
+s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
+s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
+s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
+
+s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                  u32 enable_addr);
+s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
+s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
+u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
+s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
+                              u32 addr_count, ixgbe_mc_addr_itr func);
+s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                              u32 mc_addr_count, ixgbe_mc_addr_itr func);
+s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
+s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
+s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
+s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
+                   u32 vind, bool vlan_on);
+
+s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
+
+void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
+s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
+                                   u16 *firmware_version);
+s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
+s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
+s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
+s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 
*eeprom_data);
+u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
+
+#endif /* _IXGBE_API_H_ */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_common.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_common.c  Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,1807 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#include "ixgbe_common.h"
+#include "ixgbe_api.h"
+
+static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
+static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
+static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
+static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
+static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
+static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
+                                        u16 count);
+static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
+static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
+static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
+
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
+static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
+void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
+void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
+
+/**
+ *  ixgbe_init_ops_generic - Inits function ptrs
+ *  @hw: pointer to the hardware structure
+ *
+ *  Initialize the function pointers.
+ **/
+s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
+{
+       struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+       struct ixgbe_mac_info *mac = &hw->mac;
+       u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+       /* EEPROM */
+       eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
+       /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
+       if (eec & (1 << 8))
+               eeprom->ops.read = &ixgbe_read_eeprom_generic;
+       else
+               eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
+       eeprom->ops.write = &ixgbe_write_eeprom_generic;
+       eeprom->ops.validate_checksum =
+                                     &ixgbe_validate_eeprom_checksum_generic;
+       eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
+
+       /* MAC */
+       mac->ops.init_hw = &ixgbe_init_hw_generic;
+       mac->ops.reset_hw = NULL;
+       mac->ops.start_hw = &ixgbe_start_hw_generic;
+       mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
+       mac->ops.get_media_type = NULL;
+       mac->ops.get_supported_physical_layer = NULL;
+       mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
+       mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
+       mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
+       mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
+
+       /* LEDs */
+       mac->ops.led_on = &ixgbe_led_on_generic;
+       mac->ops.led_off = &ixgbe_led_off_generic;
+       mac->ops.blink_led_start = NULL;
+       mac->ops.blink_led_stop = NULL;
+
+       /* RAR, Multicast, VLAN */
+       mac->ops.set_rar = &ixgbe_set_rar_generic;
+       mac->ops.clear_rar = &ixgbe_clear_rar_generic;
+       mac->ops.set_vmdq = NULL;
+       mac->ops.clear_vmdq = NULL;
+       mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
+       mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
+       mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
+       mac->ops.enable_mc = &ixgbe_enable_mc_generic;
+       mac->ops.disable_mc = &ixgbe_disable_mc_generic;
+       mac->ops.clear_vfta = NULL;
+       mac->ops.set_vfta = NULL;
+       mac->ops.init_uta_tables = NULL;
+
+
+       /* Link */
+       mac->ops.get_link_capabilities = NULL;
+       mac->ops.setup_link = NULL;
+       mac->ops.setup_link_speed = NULL;
+       mac->ops.check_link = NULL;
+
+       return 0;
+}
+
+/**
+ *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
+ *  @hw: pointer to hardware structure
+ *
+ *  Starts the hardware by filling the bus info structure and media type, 
clears
+ *  all on chip counters, initializes receive address registers, multicast
+ *  table, VLAN filter table, calls routine to set up link and flow control
+ *  settings, and leaves transmit and receive units disabled and uninitialized
+ **/
+s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
+{
+       u32 ctrl_ext;
+
+       /* Set the media type */
+       hw->phy.media_type = hw->mac.ops.get_media_type(hw);
+
+       /* Set bus info */
+       hw->mac.ops.get_bus_info(hw);
+
+       /* Identify the PHY */
+       hw->phy.ops.identify(hw);
+
+       /*
+        * Store MAC address from RAR0, clear receive address registers, and
+        * clear the multicast table
+        */
+       hw->mac.ops.init_rx_addrs(hw);
+
+       /* Clear the VLAN filter table */
+       hw->mac.ops.clear_vfta(hw);
+
+       /* Set up link */
+       hw->mac.ops.setup_link(hw);
+
+       /* Clear statistics registers */
+       hw->mac.ops.clear_hw_cntrs(hw);
+
+       /* Set No Snoop Disable */
+       ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
+       ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
+       IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
+       IXGBE_WRITE_FLUSH(hw);
+
+       /* Clear adapter stopped flag */
+       hw->adapter_stopped = false;
+
+       return 0;
+}
+
+/**
+ *  ixgbe_init_hw_generic - Generic hardware initialization
+ *  @hw: pointer to hardware structure
+ *
+ *  Initialize the hardware by resetting the hardware, filling the bus info
+ *  structure and media type, clears all on chip counters, initializes receive
+ *  address registers, multicast table, VLAN filter table, calls routine to set
+ *  up link and flow control settings, and leaves transmit and receive units
+ *  disabled and uninitialized
+ **/
+s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
+{
+       /* Reset the hardware */
+       hw->mac.ops.reset_hw(hw);
+
+       /* Start the HW */
+       hw->mac.ops.start_hw(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears all hardware statistics counters by reading them from the hardware
+ *  Statistics counters are clear on read.
+ **/
+s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
+{
+       u16 i = 0;
+
+       IXGBE_READ_REG(hw, IXGBE_CRCERRS);
+       IXGBE_READ_REG(hw, IXGBE_ILLERRC);
+       IXGBE_READ_REG(hw, IXGBE_ERRBC);
+       IXGBE_READ_REG(hw, IXGBE_MSPDC);
+       for (i = 0; i < 8; i++)
+               IXGBE_READ_REG(hw, IXGBE_MPC(i));
+
+       IXGBE_READ_REG(hw, IXGBE_MLFC);
+       IXGBE_READ_REG(hw, IXGBE_MRFC);
+       IXGBE_READ_REG(hw, IXGBE_RLEC);
+       IXGBE_READ_REG(hw, IXGBE_LXONTXC);
+       IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
+       IXGBE_READ_REG(hw, IXGBE_LXONRXC);
+       IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
+
+       for (i = 0; i < 8; i++) {
+               IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
+               IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
+               IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
+               IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
+       }
+       IXGBE_READ_REG(hw, IXGBE_PRC64);
+       IXGBE_READ_REG(hw, IXGBE_PRC127);
+       IXGBE_READ_REG(hw, IXGBE_PRC255);
+       IXGBE_READ_REG(hw, IXGBE_PRC511);
+       IXGBE_READ_REG(hw, IXGBE_PRC1023);
+       IXGBE_READ_REG(hw, IXGBE_PRC1522);
+       IXGBE_READ_REG(hw, IXGBE_GPRC);
+       IXGBE_READ_REG(hw, IXGBE_BPRC);
+       IXGBE_READ_REG(hw, IXGBE_MPRC);
+       IXGBE_READ_REG(hw, IXGBE_GPTC);
+       IXGBE_READ_REG(hw, IXGBE_GORCL);
+       IXGBE_READ_REG(hw, IXGBE_GORCH);
+       IXGBE_READ_REG(hw, IXGBE_GOTCL);
+       IXGBE_READ_REG(hw, IXGBE_GOTCH);
+       for (i = 0; i < 8; i++)
+               IXGBE_READ_REG(hw, IXGBE_RNBC(i));
+       IXGBE_READ_REG(hw, IXGBE_RUC);
+       IXGBE_READ_REG(hw, IXGBE_RFC);
+       IXGBE_READ_REG(hw, IXGBE_ROC);
+       IXGBE_READ_REG(hw, IXGBE_RJC);
+       IXGBE_READ_REG(hw, IXGBE_MNGPRC);
+       IXGBE_READ_REG(hw, IXGBE_MNGPDC);
+       IXGBE_READ_REG(hw, IXGBE_MNGPTC);
+       IXGBE_READ_REG(hw, IXGBE_TORL);
+       IXGBE_READ_REG(hw, IXGBE_TORH);
+       IXGBE_READ_REG(hw, IXGBE_TPR);
+       IXGBE_READ_REG(hw, IXGBE_TPT);
+       IXGBE_READ_REG(hw, IXGBE_PTC64);
+       IXGBE_READ_REG(hw, IXGBE_PTC127);
+       IXGBE_READ_REG(hw, IXGBE_PTC255);
+       IXGBE_READ_REG(hw, IXGBE_PTC511);
+       IXGBE_READ_REG(hw, IXGBE_PTC1023);
+       IXGBE_READ_REG(hw, IXGBE_PTC1522);
+       IXGBE_READ_REG(hw, IXGBE_MPTC);
+       IXGBE_READ_REG(hw, IXGBE_BPTC);
+       for (i = 0; i < 16; i++) {
+               IXGBE_READ_REG(hw, IXGBE_QPRC(i));
+               IXGBE_READ_REG(hw, IXGBE_QBRC(i));
+               IXGBE_READ_REG(hw, IXGBE_QPTC(i));
+               IXGBE_READ_REG(hw, IXGBE_QBTC(i));
+       }
+
+       return 0;
+}
+
+/**
+ *  ixgbe_read_pba_num_generic - Reads part number from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number from the EEPROM
+ *
+ *  Reads the part number from the EEPROM.
+ **/
+s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+{
+       s32 ret_val;
+       u16 data;
+
+       ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+       if (ret_val) {
+               hw_dbg(hw, "NVM Read Error\n");
+               return ret_val;
+       }
+       *pba_num = (u32)(data << 16);
+
+       ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
+       if (ret_val) {
+               hw_dbg(hw, "NVM Read Error\n");
+               return ret_val;
+       }
+       *pba_num |= data;
+
+       return 0;
+}
+
+/**
+ *  ixgbe_get_mac_addr_generic - Generic get MAC address
+ *  @hw: pointer to hardware structure
+ *  @mac_addr: Adapter MAC address
+ *
+ *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
+ *  A reset of the adapter must be performed prior to calling this function
+ *  in order for the MAC address to have been loaded from the EEPROM into RAR0
+ **/
+s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
+{
+       u32 rar_high;
+       u32 rar_low;
+       u16 i;
+
+       rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
+       rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
+
+       for (i = 0; i < 4; i++)
+               mac_addr[i] = (u8)(rar_low >> (i*8));
+
+       for (i = 0; i < 2; i++)
+               mac_addr[i+4] = (u8)(rar_high >> (i*8));
+
+       return 0;
+}
+
+/**
+ *  ixgbe_get_bus_info_generic - Generic set PCI bus info
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
+ **/
+s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
+{
+       struct ixgbe_mac_info *mac = &hw->mac;
+       u16 link_status;
+
+       hw->bus.type = ixgbe_bus_type_pci_express;
+
+       /* Get the negotiated link width and speed from PCI config space */
+       link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
+
+       switch (link_status & IXGBE_PCI_LINK_WIDTH) {
+       case IXGBE_PCI_LINK_WIDTH_1:
+               hw->bus.width = ixgbe_bus_width_pcie_x1;
+               break;
+       case IXGBE_PCI_LINK_WIDTH_2:
+               hw->bus.width = ixgbe_bus_width_pcie_x2;
+               break;
+       case IXGBE_PCI_LINK_WIDTH_4:
+               hw->bus.width = ixgbe_bus_width_pcie_x4;
+               break;
+       case IXGBE_PCI_LINK_WIDTH_8:
+               hw->bus.width = ixgbe_bus_width_pcie_x8;
+               break;
+       default:
+               hw->bus.width = ixgbe_bus_width_unknown;
+               break;
+       }
+
+       switch (link_status & IXGBE_PCI_LINK_SPEED) {
+       case IXGBE_PCI_LINK_SPEED_2500:
+               hw->bus.speed = ixgbe_bus_speed_2500;
+               break;
+       case IXGBE_PCI_LINK_SPEED_5000:
+               hw->bus.speed = ixgbe_bus_speed_5000;
+               break;
+       default:
+               hw->bus.speed = ixgbe_bus_speed_unknown;
+               break;
+       }
+
+       mac->ops.set_lan_id(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port 
devices
+ *  @hw: pointer to the HW structure
+ *
+ *  Determines the LAN function id by reading memory-mapped registers
+ *  and swaps the port value if requested.
+ **/
+void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
+{
+       struct ixgbe_bus_info *bus = &hw->bus;
+       u32 reg;
+
+       reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
+       bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
+
+       /* check for a port swap */
+       reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
+       if (reg & IXGBE_FACTPS_LFS)
+               bus->func ^= 0x1;
+}
+
+/**
+ *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
+ *  disables transmit and receive units. The adapter_stopped flag is used by
+ *  the shared code and drivers to determine if the adapter is in a stopped
+ *  state and should not touch the hardware.
+ **/
+s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
+{
+       u32 number_of_queues;
+       u32 reg_val;
+       u16 i;
+
+       /*
+        * Set the adapter_stopped flag so other driver functions stop touching
+        * the hardware
+        */
+       hw->adapter_stopped = true;
+
+       /* Disable the receive unit */
+       reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
+       reg_val &= ~(IXGBE_RXCTRL_RXEN);
+       IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
+       IXGBE_WRITE_FLUSH(hw);
+       msleep(2);
+
+       /* Clear interrupt mask to stop from interrupts being generated */
+       IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
+
+       /* Clear any pending interrupts */
+       IXGBE_READ_REG(hw, IXGBE_EICR);
+
+       /* Disable the transmit unit.  Each queue must be disabled. */
+       number_of_queues = hw->mac.max_tx_queues;
+       for (i = 0; i < number_of_queues; i++) {
+               reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
+               if (reg_val & IXGBE_TXDCTL_ENABLE) {
+                       reg_val &= ~IXGBE_TXDCTL_ENABLE;
+                       IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
+               }
+       }
+
+       /*
+        * Prevent the PCI-E bus from from hanging by disabling PCI-E master
+        * access and verify no pending requests
+        */
+       if (ixgbe_disable_pcie_master(hw) != 0)
+               hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+
+       return 0;
+}
+
+/**
+ *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn on
+ **/
+s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
+{
+       u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+
+       /* To turn on the LED, set mode to ON. */
+       led_reg &= ~IXGBE_LED_MODE_MASK(index);
+       led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
+       IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
+       IXGBE_WRITE_FLUSH(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn off
+ **/
+s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
+{
+       u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+
+       /* To turn off the LED, set mode to OFF. */
+       led_reg &= ~IXGBE_LED_MODE_MASK(index);
+       led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
+       IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
+       IXGBE_WRITE_FLUSH(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
+ *  @hw: pointer to hardware structure
+ *
+ *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
+ *  ixgbe_hw struct in order to set up EEPROM access.
+ **/
+s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
+{
+       struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+       u32 eec;
+       u16 eeprom_size;
+
+       if (eeprom->type == ixgbe_eeprom_uninitialized) {
+               eeprom->type = ixgbe_eeprom_none;
+               /* Set default semaphore delay to 10ms which is a well
+                * tested value */
+               eeprom->semaphore_delay = 10;
+
+               /*
+                * Check for EEPROM present first.
+                * If not present leave as none
+                */
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               if (eec & IXGBE_EEC_PRES) {
+                       eeprom->type = ixgbe_eeprom_spi;
+
+                       /*
+                        * SPI EEPROM is assumed here.  This code would need to
+                        * change if a future EEPROM is not SPI.
+                        */
+                       eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
+                                           IXGBE_EEC_SIZE_SHIFT);
+                       eeprom->word_size = 1 << (eeprom_size +
+                                                IXGBE_EEPROM_WORD_SIZE_SHIFT);
+               }
+
+               if (eec & IXGBE_EEC_ADDR_SIZE)
+                       eeprom->address_bits = 16;
+               else
+                       eeprom->address_bits = 8;
+               hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
+                         "%d\n", eeprom->type, eeprom->word_size,
+                         eeprom->address_bits);
+       }
+
+       return 0;
+}
+
+/**
+ *  ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @data: 16 bit word to be written to the EEPROM
+ *
+ *  If ixgbe_eeprom_update_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
+{
+       s32 status;
+       u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
+
+       hw->eeprom.ops.init_params(hw);
+
+       if (offset >= hw->eeprom.word_size) {
+               status = IXGBE_ERR_EEPROM;
+               goto out;
+       }
+
+       /* Prepare the EEPROM for writing  */
+       status = ixgbe_acquire_eeprom(hw);
+
+       if (status == 0) {
+               if (ixgbe_ready_eeprom(hw) != 0) {
+                       ixgbe_release_eeprom(hw);
+                       status = IXGBE_ERR_EEPROM;
+               }
+       }
+
+       if (status == 0) {
+               ixgbe_standby_eeprom(hw);
+
+               /*  Send the WRITE ENABLE command (8 bit opcode )  */
+               ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
+                                           IXGBE_EEPROM_OPCODE_BITS);
+
+               ixgbe_standby_eeprom(hw);
+
+               /*
+                * Some SPI eeproms use the 8th address bit embedded in the
+                * opcode
+                */
+               if ((hw->eeprom.address_bits == 8) && (offset >= 128))
+                       write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
+
+               /* Send the Write command (8-bit opcode + addr) */
+               ixgbe_shift_out_eeprom_bits(hw, write_opcode,
+                                           IXGBE_EEPROM_OPCODE_BITS);
+               ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
+                                           hw->eeprom.address_bits);
+
+               /* Send the data */
+               data = (data >> 8) | (data << 8);
+               ixgbe_shift_out_eeprom_bits(hw, data, 16);
+               ixgbe_standby_eeprom(hw);
+
+               msleep(hw->eeprom.semaphore_delay);
+               /* Done with writing - release the EEPROM */
+               ixgbe_release_eeprom(hw);
+       }
+
+out:
+       return status;
+}
+
+/**
+ *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be read
+ *  @data: read 16 bit value from EEPROM
+ *
+ *  Reads 16 bit value from EEPROM through bit-bang method
+ **/
+s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+                                       u16 *data)
+{
+       s32 status;
+       u16 word_in;
+       u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
+
+       hw->eeprom.ops.init_params(hw);
+
+       if (offset >= hw->eeprom.word_size) {
+               status = IXGBE_ERR_EEPROM;
+               goto out;
+       }
+
+       /* Prepare the EEPROM for reading  */
+       status = ixgbe_acquire_eeprom(hw);
+
+       if (status == 0) {
+               if (ixgbe_ready_eeprom(hw) != 0) {
+                       ixgbe_release_eeprom(hw);
+                       status = IXGBE_ERR_EEPROM;
+               }
+       }
+
+       if (status == 0) {
+               ixgbe_standby_eeprom(hw);
+
+               /*
+                * Some SPI eeproms use the 8th address bit embedded in the
+                * opcode
+                */
+               if ((hw->eeprom.address_bits == 8) && (offset >= 128))
+                       read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
+
+               /* Send the READ command (opcode + addr) */
+               ixgbe_shift_out_eeprom_bits(hw, read_opcode,
+                                           IXGBE_EEPROM_OPCODE_BITS);
+               ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
+                                           hw->eeprom.address_bits);
+
+               /* Read the data. */
+               word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
+               *data = (word_in >> 8) | (word_in << 8);
+
+               /* End this read operation */
+               ixgbe_release_eeprom(hw);
+       }
+
+out:
+       return status;
+}
+
+/**
+ *  ixgbe_read_eeprom_generic - Read EEPROM word using EERD
+ *  @hw: pointer to hardware structure
+ *  @offset: offset of  word in the EEPROM to read
+ *  @data: word read from the EEPROM
+ *
+ *  Reads a 16 bit word from the EEPROM using the EERD register.
+ **/
+s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
+{
+       u32 eerd;
+       s32 status;
+
+       hw->eeprom.ops.init_params(hw);
+
+       if (offset >= hw->eeprom.word_size) {
+               status = IXGBE_ERR_EEPROM;
+               goto out;
+       }
+
+       eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
+              IXGBE_EEPROM_READ_REG_START;
+
+       IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
+       status = ixgbe_poll_eeprom_eerd_done(hw);
+
+       if (status == 0)
+               *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
+                        IXGBE_EEPROM_READ_REG_DATA);
+       else
+               hw_dbg(hw, "Eeprom read timed out\n");
+
+out:
+       return status;
+}
+
+/**
+ *  ixgbe_poll_eeprom_eerd_done - Poll EERD status
+ *  @hw: pointer to hardware structure
+ *
+ *  Polls the status bit (bit 1) of the EERD to determine when the read is 
done.
+ **/
+static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
+{
+       u32 i;
+       u32 reg;
+       s32 status = IXGBE_ERR_EEPROM;
+
+       for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
+               reg = IXGBE_READ_REG(hw, IXGBE_EERD);
+               if (reg & IXGBE_EEPROM_READ_REG_DONE) {
+                       status = 0;
+                       break;
+               }
+               udelay(5);
+       }
+       return status;
+}
+
+/**
+ *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
+ *  @hw: pointer to hardware structure
+ *
+ *  Prepares EEPROM for access using bit-bang method. This function should
+ *  be called before issuing a command to the EEPROM.
+ **/
+static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
+{
+       s32 status = 0;
+       u32 eec;
+       u32 i;
+
+       if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
+               status = IXGBE_ERR_SWFW_SYNC;
+
+       if (status == 0) {
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+               /* Request EEPROM Access */
+               eec |= IXGBE_EEC_REQ;
+               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+
+               for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
+                       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+                       if (eec & IXGBE_EEC_GNT)
+                               break;
+                       udelay(5);
+               }
+
+               /* Release if grant not acquired */
+               if (!(eec & IXGBE_EEC_GNT)) {
+                       eec &= ~IXGBE_EEC_REQ;
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                       hw_dbg(hw, "Could not acquire EEPROM grant\n");
+
+                       ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+                       status = IXGBE_ERR_EEPROM;
+               }
+       }
+
+       /* Setup EEPROM for Read/Write */
+       if (status == 0) {
+               /* Clear CS and SK */
+               eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
+               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_FLUSH(hw);
+               udelay(1);
+       }
+       return status;
+}
+
+/**
+ *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
+ **/
+static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
+{
+       s32 status = IXGBE_ERR_EEPROM;
+       u32 timeout;
+       u32 i;
+       u32 swsm;
+
+       /* Set timeout value based on size of EEPROM */
+       timeout = hw->eeprom.word_size + 1;
+
+       /* Get SMBI software semaphore between device drivers first */
+       for (i = 0; i < timeout; i++) {
+               /*
+                * If the SMBI bit is 0 when we read it, then the bit will be
+                * set and we have the semaphore
+                */
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               if (!(swsm & IXGBE_SWSM_SMBI)) {
+                       status = 0;
+                       break;
+               }
+               msleep(1);
+       }
+
+       /* Now get the semaphore between SW/FW through the SWESMBI bit */
+       if (status == 0) {
+               for (i = 0; i < timeout; i++) {
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+
+                       /* Set the SW EEPROM semaphore bit to request access */
+                       swsm |= IXGBE_SWSM_SWESMBI;
+                       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+
+                       /*
+                        * If we set the bit successfully then we got the
+                        * semaphore.
+                        */
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                       if (swsm & IXGBE_SWSM_SWESMBI)
+                               break;
+
+                       udelay(50);
+               }
+
+               /*
+                * Release semaphores and return error if SW EEPROM semaphore
+                * was not granted because we don't have access to the EEPROM
+                */
+               if (i >= timeout) {
+                       hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
+                                "not granted.\n");
+                       ixgbe_release_eeprom_semaphore(hw);
+                       status = IXGBE_ERR_EEPROM;
+               }
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
+ *  @hw: pointer to hardware structure
+ *
+ *  This function clears hardware semaphore bits.
+ **/
+static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
+{
+       u32 swsm;
+
+       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+
+       /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
+       swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
+       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+       IXGBE_WRITE_FLUSH(hw);
+}
+
+/**
+ *  ixgbe_ready_eeprom - Polls for EEPROM ready
+ *  @hw: pointer to hardware structure
+ **/
+static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
+{
+       s32 status = 0;
+       u16 i;
+       u8 spi_stat_reg;
+
+       /*
+        * Read "Status Register" repeatedly until the LSB is cleared.  The
+        * EEPROM will signal that the command has been completed by clearing
+        * bit 0 of the internal status register.  If it's not cleared within
+        * 5 milliseconds, then error out.
+        */
+       for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
+               ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
+                                           IXGBE_EEPROM_OPCODE_BITS);
+               spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
+               if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
+                       break;
+
+               udelay(5);
+               ixgbe_standby_eeprom(hw);
+       };
+
+       /*
+        * On some parts, SPI write time could vary from 0-20mSec on 3.3V
+        * devices (and only 0-5mSec on 5V devices)
+        */
+       if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
+               hw_dbg(hw, "SPI EEPROM Status error\n");
+               status = IXGBE_ERR_EEPROM;
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
+{
+       u32 eec;
+
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+       /* Toggle CS to flush commands */
+       eec |= IXGBE_EEC_CS;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(1);
+       eec &= ~IXGBE_EEC_CS;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(1);
+}
+
+/**
+ *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
+ *  @hw: pointer to hardware structure
+ *  @data: data to send to the EEPROM
+ *  @count: number of bits to shift out
+ **/
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
+                                        u16 count)
+{
+       u32 eec;
+       u32 mask;
+       u32 i;
+
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+       /*
+        * Mask is used to shift "count" bits of "data" out to the EEPROM
+        * one bit at a time.  Determine the starting bit based on count
+        */
+       mask = 0x01 << (count - 1);
+
+       for (i = 0; i < count; i++) {
+               /*
+                * A "1" is shifted out to the EEPROM by setting bit "DI" to a
+                * "1", and then raising and then lowering the clock (the SK
+                * bit controls the clock input to the EEPROM).  A "0" is
+                * shifted out to the EEPROM by setting "DI" to "0" and then
+                * raising and then lowering the clock.
+                */
+               if (data & mask)
+                       eec |= IXGBE_EEC_DI;
+               else
+                       eec &= ~IXGBE_EEC_DI;
+
+               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_FLUSH(hw);
+
+               udelay(1);
+
+               ixgbe_raise_eeprom_clk(hw, &eec);
+               ixgbe_lower_eeprom_clk(hw, &eec);
+
+               /*
+                * Shift mask to signify next bit of data to shift in to the
+                * EEPROM
+                */
+               mask = mask >> 1;
+       };
+
+       /* We leave the "DI" bit set to "0" when we leave this routine. */
+       eec &= ~IXGBE_EEC_DI;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_FLUSH(hw);
+}
+
+/**
+ *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
+ *  @hw: pointer to hardware structure
+ **/
+static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
+{
+       u32 eec;
+       u32 i;
+       u16 data = 0;
+
+       /*
+        * In order to read a register from the EEPROM, we need to shift
+        * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
+        * the clock input to the EEPROM (setting the SK bit), and then reading
+        * the value of the "DO" bit.  During this "shifting in" process the
+        * "DI" bit should always be clear.
+        */
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+       eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
+
+       for (i = 0; i < count; i++) {
+               data = data << 1;
+               ixgbe_raise_eeprom_clk(hw, &eec);
+
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+               eec &= ~(IXGBE_EEC_DI);
+               if (eec & IXGBE_EEC_DO)
+                       data |= 1;
+
+               ixgbe_lower_eeprom_clk(hw, &eec);
+       }
+
+       return data;
+}
+
+/**
+ *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eec: EEC register's current value
+ **/
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+{
+       /*
+        * Raise the clock input to the EEPROM
+        * (setting the SK bit), then delay
+        */
+       *eec = *eec | IXGBE_EEC_SK;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(1);
+}
+
+/**
+ *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eecd: EECD's current value
+ **/
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+{
+       /*
+        * Lower the clock input to the EEPROM (clearing the SK bit), then
+        * delay
+        */
+       *eec = *eec & ~IXGBE_EEC_SK;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_FLUSH(hw);
+       udelay(1);
+}
+
+/**
+ *  ixgbe_release_eeprom - Release EEPROM, release semaphores
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
+{
+       u32 eec;
+
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+       eec |= IXGBE_EEC_CS;  /* Pull CS high */
+       eec &= ~IXGBE_EEC_SK; /* Lower SCK */
+
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_FLUSH(hw);
+
+       udelay(1);
+
+       /* Stop requesting EEPROM access */
+       eec &= ~IXGBE_EEC_REQ;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+
+       ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
+}
+
+/**
+ *  ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
+ *  @hw: pointer to hardware structure
+ **/
+static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
+{
+       u16 i;
+       u16 j;
+       u16 checksum = 0;
+       u16 length = 0;
+       u16 pointer = 0;
+       u16 word = 0;
+
+       /* Include 0x0-0x3F in the checksum */
+       for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
+               if (hw->eeprom.ops.read(hw, i, &word) != 0) {
+                       hw_dbg(hw, "EEPROM read failed\n");
+                       break;
+               }
+               checksum += word;
+       }
+
+       /* Include all data from pointers except for the fw pointer */
+       for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
+               hw->eeprom.ops.read(hw, i, &pointer);
+
+               /* Make sure the pointer seems valid */
+               if (pointer != 0xFFFF && pointer != 0) {
+                       hw->eeprom.ops.read(hw, pointer, &length);
+
+                       if (length != 0xFFFF && length != 0) {
+                               for (j = pointer+1; j <= pointer+length; j++) {
+                                       hw->eeprom.ops.read(hw, j, &word);
+                                       checksum += word;
+                               }
+                       }
+               }
+       }
+
+       checksum = (u16)IXGBE_EEPROM_SUM - checksum;
+
+       return checksum;
+}
+
+/**
+ *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
+ *  @hw: pointer to hardware structure
+ *  @checksum_val: calculated checksum
+ *
+ *  Performs checksum calculation and validates the EEPROM checksum.  If the
+ *  caller does not need checksum_val, the value can be NULL.
+ **/
+s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           u16 *checksum_val)
+{
+       s32 status;
+       u16 checksum;
+       u16 read_checksum = 0;
+
+       /*
+        * Read the first word from the EEPROM. If this times out or fails, do
+        * not continue or we could be in for a very long wait while every
+        * EEPROM read fails
+        */
+       status = hw->eeprom.ops.read(hw, 0, &checksum);
+
+       if (status == 0) {
+               checksum = ixgbe_calc_eeprom_checksum(hw);
+
+               hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
+
+               /*
+                * Verify read checksum from EEPROM is the same as
+                * calculated checksum
+                */
+               if (read_checksum != checksum)
+                       status = IXGBE_ERR_EEPROM_CHECKSUM;
+
+               /* If the user cares, return the calculated checksum */
+               if (checksum_val)
+                       *checksum_val = checksum;
+       } else {
+               hw_dbg(hw, "EEPROM read failed\n");
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
+{
+       s32 status;
+       u16 checksum;
+
+       /*
+        * Read the first word from the EEPROM. If this times out or fails, do
+        * not continue or we could be in for a very long wait while every
+        * EEPROM read fails
+        */
+       status = hw->eeprom.ops.read(hw, 0, &checksum);
+
+       if (status == 0) {
+               checksum = ixgbe_calc_eeprom_checksum(hw);
+               status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
+                                             checksum);
+       } else {
+               hw_dbg(hw, "EEPROM read failed\n");
+       }
+
+       return status;
+}
+
+/**
+ *  ixgbe_validate_mac_addr - Validate MAC address
+ *  @mac_addr: pointer to MAC address.
+ *
+ *  Tests a MAC address to ensure it is a valid Individual Address
+ **/
+s32 ixgbe_validate_mac_addr(u8 *mac_addr)
+{
+       s32 status = 0;
+
+       /* Make sure it is not a multicast address */
+       if (IXGBE_IS_MULTICAST(mac_addr)) {
+               hw_dbg(hw, "MAC address is multicast\n");
+               status = IXGBE_ERR_INVALID_MAC_ADDR;
+       /* Not a broadcast address */
+       } else if (IXGBE_IS_BROADCAST(mac_addr)) {
+               hw_dbg(hw, "MAC address is broadcast\n");
+               status = IXGBE_ERR_INVALID_MAC_ADDR;
+       /* Reject the zero address */
+       } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
+                  mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
+               hw_dbg(hw, "MAC address is all zeros\n");
+               status = IXGBE_ERR_INVALID_MAC_ADDR;
+       }
+       return status;
+}
+
+/**
+ *  ixgbe_set_rar_generic - Set Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq "set" or "pool" index
+ *  @enable_addr: set flag that address is active
+ *
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                          u32 enable_addr)
+{
+       u32 rar_low, rar_high;
+       u32 rar_entries = hw->mac.num_rar_entries;
+
+       /* setup VMDq pool selection before this RAR gets enabled */
+       hw->mac.ops.set_vmdq(hw, index, vmdq);
+
+       /* Make sure we are using a valid rar index range */
+       if (index < rar_entries) {
+               /*
+                * HW expects these in little endian so we reverse the byte
+                * order from network order (big endian) to little endian
+                */
+               rar_low = ((u32)addr[0] |
+                          ((u32)addr[1] << 8) |
+                          ((u32)addr[2] << 16) |
+                          ((u32)addr[3] << 24));
+               /*
+                * Some parts put the VMDq setting in the extra RAH bits,
+                * so save everything except the lower 16 bits that hold part
+                * of the address and the address valid bit.
+                */
+               rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+               rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+               rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
+
+               if (enable_addr != 0)
+                       rar_high |= IXGBE_RAH_AV;
+
+               IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
+               IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+       } else {
+               hw_dbg(hw, "RAR index %d is out of range.\n", index);
+       }
+
+       return 0;
+}
+
+/**
+ *  ixgbe_clear_rar_generic - Remove Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *
+ *  Clears an ethernet address from a receive address register.
+ **/
+s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
+{
+       u32 rar_high;
+       u32 rar_entries = hw->mac.num_rar_entries;
+
+       /* Make sure we are using a valid rar index range */
+       if (index < rar_entries) {
+               /*
+                * Some parts put the VMDq setting in the extra RAH bits,
+                * so save everything except the lower 16 bits that hold part
+                * of the address and the address valid bit.
+                */
+               rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+               rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+
+               IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+       } else {
+               hw_dbg(hw, "RAR index %d is out of range.\n", index);
+       }
+
+       /* clear VMDq pool/queue selection for this RAR */
+       hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_enable_rar - Enable Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: index into the RAR table
+ *
+ *  Enables the select receive address register.
+ **/
+static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
+{
+       u32 rar_high;
+
+       rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+       rar_high |= IXGBE_RAH_AV;
+       IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+}
+
+/**
+ *  ixgbe_disable_rar - Disable Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: index into the RAR table
+ *
+ *  Disables the select receive address register.
+ **/
+static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
+{
+       u32 rar_high;
+
+       rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+       rar_high &= (~IXGBE_RAH_AV);
+       IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+}
+
+/**
+ *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
+ *  @hw: pointer to hardware structure
+ *
+ *  Places the MAC address in receive address register 0 and clears the rest
+ *  of the receive address registers. Clears the multicast table. Assumes
+ *  the receiver is in reset when the routine is called.
+ **/
+s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
+{
+       u32 i;
+       u32 rar_entries = hw->mac.num_rar_entries;
+
+       /*
+        * If the current mac address is valid, assume it is a software override
+        * to the permanent address.
+        * Otherwise, use the permanent address from the eeprom.
+        */
+       if (ixgbe_validate_mac_addr(hw->mac.addr) ==
+           IXGBE_ERR_INVALID_MAC_ADDR) {
+               /* Get the MAC address from the RAR0 for later reference */
+               hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
+
+               hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
+                         hw->mac.addr[0], hw->mac.addr[1],
+                         hw->mac.addr[2]);
+               hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
+                         hw->mac.addr[4], hw->mac.addr[5]);
+       } else {
+               /* Setup the receive address. */
+               hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
+               hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
+                         hw->mac.addr[0], hw->mac.addr[1],
+                         hw->mac.addr[2]);
+               hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
+                         hw->mac.addr[4], hw->mac.addr[5]);
+
+               hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
+       }
+       hw->addr_ctrl.overflow_promisc = 0;
+
+       hw->addr_ctrl.rar_used_count = 1;
+
+       /* Zero out the other receive addresses. */
+       hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
+       for (i = 1; i < rar_entries; i++) {
+               IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
+       }
+
+       /* Clear the MTA */
+       hw->addr_ctrl.mc_addr_in_rar_count = 0;
+       hw->addr_ctrl.mta_in_use = 0;
+       IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
+
+       hw_dbg(hw, " Clearing MTA\n");
+       for (i = 0; i < hw->mac.mcft_size; i++)
+               IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
+
+       ixgbe_init_uta_tables(hw);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_add_uc_addr - Adds a secondary unicast address.
+ *  @hw: pointer to hardware structure
+ *  @addr: new address
+ *
+ *  Adds it to unused receive address register or goes into promiscuous mode.
+ **/
+void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
+{
+       u32 rar_entries = hw->mac.num_rar_entries;
+       u32 rar;
+
+       hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
+                 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+       /*
+        * Place this address in the RAR if there is room,
+        * else put the controller into promiscuous mode
+        */
+       if (hw->addr_ctrl.rar_used_count < rar_entries) {
+               rar = hw->addr_ctrl.rar_used_count -
+                     hw->addr_ctrl.mc_addr_in_rar_count;
+               hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
+               hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
+               hw->addr_ctrl.rar_used_count++;
+       } else {
+               hw->addr_ctrl.overflow_promisc++;
+       }
+
+       hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
+}
+
+/**
+ *  ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
+ *  @hw: pointer to hardware structure
+ *  @addr_list: the list of new addresses
+ *  @addr_count: number of addresses
+ *  @next: iterator function to walk the address list
+ *
+ *  The given list replaces any existing list.  Clears the secondary addrs from
+ *  receive address registers.  Uses unused receive address registers for the
+ *  first secondary addresses, and falls back to promiscuous mode as needed.
+ *
+ *  Drivers using secondary unicast addresses must set user_set_promisc when
+ *  manually putting the device into promiscuous mode.
+ **/
+s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
+                                      u32 addr_count, ixgbe_mc_addr_itr next)
+{
+       u8 *addr;
+       u32 i;
+       u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
+       u32 uc_addr_in_use;
+       u32 fctrl;
+       u32 vmdq;
+
+       /*
+        * Clear accounting of old secondary address list,
+        * don't count RAR[0]
+        */
+       uc_addr_in_use = hw->addr_ctrl.rar_used_count -
+                        hw->addr_ctrl.mc_addr_in_rar_count - 1;
+       hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
+       hw->addr_ctrl.overflow_promisc = 0;
+
+       /* Zero out the other receive addresses */
+       hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
+       for (i = 1; i <= uc_addr_in_use; i++) {
+               IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
+       }
+
+       /* Add the new addresses */
+       for (i = 0; i < addr_count; i++) {
+               hw_dbg(hw, " Adding the secondary addresses:\n");
+               addr = next(hw, &addr_list, &vmdq);
+               ixgbe_add_uc_addr(hw, addr, vmdq);
+       }
+
+       if (hw->addr_ctrl.overflow_promisc) {
+               /* enable promisc if not already in overflow or set by user */
+               if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
+                       hw_dbg(hw, " Entering address overflow promisc mode\n");
+                       fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+                       fctrl |= IXGBE_FCTRL_UPE;
+                       IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
+               }
+       } else {
+               /* only disable if set by overflow, not by user */
+               if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
+                       hw_dbg(hw, " Leaving address overflow promisc mode\n");
+                       fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+                       fctrl &= ~IXGBE_FCTRL_UPE;
+                       IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
+               }
+       }
+
+       hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
+       return 0;
+}
+
+/**
+ *  ixgbe_mta_vector - Determines bit-vector in multicast table to set
+ *  @hw: pointer to hardware structure
+ *  @mc_addr: the multicast address
+ *
+ *  Extracts the 12 bits, from a multicast address, to determine which
+ *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
+ *  incoming rx multicast addresses, to determine the bit-vector to check in
+ *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
+ *  by the MO field of the MCSTCTRL. The MO field is set during initialization
+ *  to mc_filter_type.
+ **/
+static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
+{
+       u32 vector = 0;
+
+       switch (hw->mac.mc_filter_type) {
+       case 0:   /* use bits [47:36] of the address */
+               vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
+               break;
+       case 1:   /* use bits [46:35] of the address */
+               vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
+               break;
+       case 2:   /* use bits [45:34] of the address */
+               vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
+               break;
+       case 3:   /* use bits [43:32] of the address */
+               vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
+               break;
+       default:  /* Invalid mc_filter_type */
+               hw_dbg(hw, "MC filter type param set incorrectly\n");
+               break;
+       }
+
+       /* vector can only be 12-bits or boundary will be exceeded */
+       vector &= 0xFFF;
+       return vector;
+}
+
+/**
+ *  ixgbe_set_mta - Set bit-vector in multicast table
+ *  @hw: pointer to hardware structure
+ *  @hash_value: Multicast address hash value
+ *
+ *  Sets the bit-vector in the multicast table.
+ **/
+void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
+{
+       u32 vector;
+       u32 vector_bit;
+       u32 vector_reg;
+       u32 mta_reg;
+
+       hw->addr_ctrl.mta_in_use++;
+
+       vector = ixgbe_mta_vector(hw, mc_addr);
+       hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
+
+       /*
+        * The MTA is a register array of 128 32-bit registers. It is treated
+        * like an array of 4096 bits.  We want to set bit
+        * BitArray[vector_value]. So we figure out what register the bit is
+        * in, read it, OR in the new bit, then write back the new value.  The
+        * register is determined by the upper 7 bits of the vector value and
+        * the bit within that register are determined by the lower 5 bits of
+        * the value.
+        */
+       vector_reg = (vector >> 5) & 0x7F;
+       vector_bit = vector & 0x1F;
+       mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
+       mta_reg |= (1 << vector_bit);
+       IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
+}
+
+/**
+ *  ixgbe_add_mc_addr - Adds a multicast address.
+ *  @hw: pointer to hardware structure
+ *  @mc_addr: new multicast address
+ *
+ *  Adds it to unused receive address register or to the multicast table.
+ **/
+void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
+{
+       u32 rar_entries = hw->mac.num_rar_entries;
+       u32 rar;
+
+       hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
+                 mc_addr[0], mc_addr[1], mc_addr[2],
+                 mc_addr[3], mc_addr[4], mc_addr[5]);
+
+       /*
+        * Place this multicast address in the RAR if there is room,
+        * else put it in the MTA
+        */
+       if (hw->addr_ctrl.rar_used_count < rar_entries) {
+               /* use RAR from the end up for multicast */
+               rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1;
+               hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
+               hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar);
+               hw->addr_ctrl.rar_used_count++;
+               hw->addr_ctrl.mc_addr_in_rar_count++;
+       } else {
+               ixgbe_set_mta(hw, mc_addr);
+       }
+
+       hw_dbg(hw, "ixgbe_add_mc_addr Complete\n");
+}
+
+/**
+ *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
+ *  @hw: pointer to hardware structure
+ *  @mc_addr_list: the list of new multicast addresses
+ *  @mc_addr_count: number of addresses
+ *  @next: iterator function to walk the multicast address list
+ *
+ *  The given list replaces any existing list. Clears the MC addrs from receive
+ *  address registers and the multicast table. Uses unused receive address
+ *  registers for the first multicast addresses, and hashes the rest into the
+ *  multicast table.
+ **/
+s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                                      u32 mc_addr_count, ixgbe_mc_addr_itr 
next)
+{
+       u32 i;
+       u32 rar_entries = hw->mac.num_rar_entries;
+       u32 vmdq;
+
+       /*
+        * Set the new number of MC addresses that we are being requested to
+        * use.
+        */
+       hw->addr_ctrl.num_mc_addrs = mc_addr_count;
+       hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
+       hw->addr_ctrl.mc_addr_in_rar_count = 0;
+       hw->addr_ctrl.mta_in_use = 0;
+
+       /* Zero out the other receive addresses. */
+       hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count,
+                 rar_entries - 1);
+       for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
+               IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
+       }
+
+       /* Clear the MTA */
+       hw_dbg(hw, " Clearing MTA\n");
+       for (i = 0; i < hw->mac.mcft_size; i++)
+               IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
+
+       /* Add the new addresses */
+       for (i = 0; i < mc_addr_count; i++) {
+               hw_dbg(hw, " Adding the multicast addresses:\n");
+               ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq));
+       }
+
+       /* Enable mta */
+       if (hw->addr_ctrl.mta_in_use > 0)
+               IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
+                               IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
+
+       hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
+       return 0;
+}
+
+/**
+ *  ixgbe_enable_mc_generic - Enable multicast address in RAR
+ *  @hw: pointer to hardware structure
+ *
+ *  Enables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
+{
+       u32 i;
+       u32 rar_entries = hw->mac.num_rar_entries;
+       struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
+
+       if (a->mc_addr_in_rar_count > 0)
+               for (i = (rar_entries - a->mc_addr_in_rar_count);
+                    i < rar_entries; i++)
+                       ixgbe_enable_rar(hw, i);
+
+       if (a->mta_in_use > 0)
+               IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
+                               hw->mac.mc_filter_type);
+
+       return 0;
+}
+
+/**
+ *  ixgbe_disable_mc_generic - Disable multicast address in RAR
+ *  @hw: pointer to hardware structure
+ *
+ *  Disables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
+{
+       u32 i;
+       u32 rar_entries = hw->mac.num_rar_entries;
+       struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
+
+       if (a->mc_addr_in_rar_count > 0)
+               for (i = (rar_entries - a->mc_addr_in_rar_count);
+                    i < rar_entries; i++)
+                       ixgbe_disable_rar(hw, i);
+
+       if (a->mta_in_use > 0)
+               IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
+
+       return 0;
+}
+
+
+
+
+/**
+ *  ixgbe_disable_pcie_master - Disable PCI-express master access
+ *  @hw: pointer to hardware structure
+ *
+ *  Disables PCI-Express master access and verifies there are no pending
+ *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
+ *  bit hasn't caused the master requests to be disabled, else 0
+ *  is returned signifying master requests disabled.
+ **/
+s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
+{
+       u32 i;
+       u32 reg_val;
+       u32 number_of_queues;
+       s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
+
+       /* Disable the receive unit by stopping each queue */
+       number_of_queues = hw->mac.max_rx_queues;
+       for (i = 0; i < number_of_queues; i++) {
+               reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
+               if (reg_val & IXGBE_RXDCTL_ENABLE) {
+                       reg_val &= ~IXGBE_RXDCTL_ENABLE;
+                       IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
+               }
+       }
+
+       reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
+       reg_val |= IXGBE_CTRL_GIO_DIS;
+       IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
+
+       for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
+               if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
+                       status = 0;
+                       break;
+               }
+               udelay(100);
+       }
+
+       return status;
+}
+
+
+/**
+ *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to acquire
+ *
+ *  Acquires the SWFW semaphore thought the GSSR register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+{
+       u32 gssr;
+       u32 swmask = mask;
+       u32 fwmask = mask << 5;
+       s32 timeout = 200;
+
+       while (timeout) {
+               if (ixgbe_get_eeprom_semaphore(hw))
+                       return -IXGBE_ERR_SWFW_SYNC;
+
+               gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
+               if (!(gssr & (fwmask | swmask)))
+                       break;
+
+               /*
+                * Firmware currently using resource (fwmask) or other software
+                * thread currently using resource (swmask)
+                */
+               ixgbe_release_eeprom_semaphore(hw);
+               msleep(5);
+               timeout--;
+       }
+
+       if (!timeout) {
+               hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
+               return -IXGBE_ERR_SWFW_SYNC;
+       }
+
+       gssr |= swmask;
+       IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
+
+       ixgbe_release_eeprom_semaphore(hw);
+       return 0;
+}
+
+/**
+ *  ixgbe_release_swfw_sync - Release SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to release
+ *
+ *  Releases the SWFW semaphore thought the GSSR register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+{
+       u32 gssr;
+       u32 swmask = mask;
+
+       ixgbe_get_eeprom_semaphore(hw);
+
+       gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
+       gssr &= ~swmask;
+       IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
+
+       ixgbe_release_eeprom_semaphore(hw);
+}
+
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_common.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_common.h  Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,77 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _IXGBE_COMMON_H_
+#define _IXGBE_COMMON_H_
+
+#include "ixgbe_type.h"
+
+s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
+s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
+s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
+s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
+s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
+s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
+s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
+void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
+s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
+
+s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
+
+s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
+s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
+s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+                                       u16 *data);
+s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           u16 *checksum_val);
+s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
+
+s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                          u32 enable_addr);
+s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
+s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
+s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                                      u32 mc_addr_count,
+                                      ixgbe_mc_addr_itr func);
+s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
+                                      u32 addr_count, ixgbe_mc_addr_itr func);
+s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
+s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
+
+s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num);
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num);
+
+s32 ixgbe_validate_mac_addr(u8 *mac_addr);
+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
+s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
+
+s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val);
+s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
+#endif /* IXGBE_COMMON */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_dcb.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_dcb.c     Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,333 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+
+#include "ixgbe_type.h"
+#include "ixgbe_dcb.h"
+#include "ixgbe_dcb_82598.h"
+
+/**
+ * ixgbe_dcb_config - Struct containing DCB settings.
+ * @dcb_config: Pointer to DCB config structure
+ *
+ * This function checks DCB rules for DCB settings.
+ * The following rules are checked:
+ * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
+ * 2. The sum of bandwidth percentages of all Traffic Classes within a 
Bandwidth
+ *    Group must total 100.
+ * 3. A Traffic Class should not be set to both Link Strict Priority
+ *    and Group Strict Priority.
+ * 4. Link strict Bandwidth Groups can only have link strict traffic classes
+ *    with zero bandwidth.
+ */
+s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *dcb_config)
+{
+       struct tc_bw_alloc *p;
+       s32 ret_val = 0;
+       u8 i, j, bw = 0, bw_id;
+       u8 bw_sum[2][MAX_BW_GROUP];
+       bool link_strict[2][MAX_BW_GROUP];
+
+       memset(bw_sum, 0, sizeof(bw_sum));
+       memset(link_strict, 0, sizeof(link_strict));
+
+       /* First Tx, then Rx */
+       for (i = 0; i < 2; i++) {
+               /* Check each traffic class for rule violation */
+               for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
+                       p = &dcb_config->tc_config[j].path[i];
+
+                       bw = p->bwg_percent;
+                       bw_id = p->bwg_id;
+
+                       if (bw_id >= MAX_BW_GROUP) {
+                               ret_val = DCB_ERR_CONFIG;
+                               goto err_config;
+                       }
+                       if (p->prio_type == prio_link) {
+                               link_strict[i][bw_id] = true;
+                               /* Link strict should have zero bandwidth */
+                               if (bw) {
+                                       ret_val = DCB_ERR_LS_BW_NONZERO;
+                                       goto err_config;
+                               }
+                       } else if (!bw) {
+                               /*
+                                * Traffic classes without link strict
+                                * should have non-zero bandwidth.
+                                */
+                               ret_val = DCB_ERR_TC_BW_ZERO;
+                               goto err_config;
+                       }
+                       bw_sum[i][bw_id] += bw;
+               }
+
+               bw = 0;
+
+               /* Check each bandwidth group for rule violation */
+               for (j = 0; j < MAX_BW_GROUP; j++) {
+                       bw += dcb_config->bw_percentage[i][j];
+                       /*
+                        * Sum of bandwidth percentages of all traffic classes
+                        * within a Bandwidth Group must total 100 except for
+                        * link strict group (zero bandwidth).
+                        */
+                       if (link_strict[i][j]) {
+                               if (bw_sum[i][j]) {
+                                       /*
+                                        * Link strict group should have zero
+                                        * bandwidth.
+                                        */
+                                       ret_val = DCB_ERR_LS_BWG_NONZERO;
+                                       goto err_config;
+                               }
+                       } else if (bw_sum[i][j] != BW_PERCENT &&
+                                  bw_sum[i][j] != 0) {
+                               ret_val = DCB_ERR_TC_BW;
+                               goto err_config;
+                       }
+               }
+
+               if (bw != BW_PERCENT) {
+                       ret_val = DCB_ERR_BW_GROUP;
+                       goto err_config;
+               }
+       }
+
+       return DCB_SUCCESS;
+
+err_config:
+       hw_dbg(hw, "DCB error code %d while checking %s settings.\n",
+                 ret_val, (j == DCB_TX_CONFIG) ? "Tx" : "Rx");
+
+       return ret_val;
+}
+
+/**
+ * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
+ * @ixgbe_dcb_config: Struct containing DCB settings.
+ * @direction: Configuring either Tx or Rx.
+ *
+ * This function calculates the credits allocated to each traffic class.
+ * It should be called only after the rules are checked by
+ * ixgbe_dcb_check_config().
+ */
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
+                                   u8 direction)
+{
+       struct tc_bw_alloc *p;
+       s32 ret_val = 0;
+       /* Initialization values default for Tx settings */
+       u32 credit_refill       = 0;
+       u32 credit_max          = 0;
+       u16 link_percentage     = 0;
+       u8  bw_percent          = 0;
+       u8  i;
+
+       if (dcb_config == NULL) {
+               ret_val = DCB_ERR_CONFIG;
+               goto out;
+       }
+
+       /* Find out the link percentage for each TC first */
+       for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+               p = &dcb_config->tc_config[i].path[direction];
+               bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
+
+               link_percentage = p->bwg_percent;
+               /* Must be careful of integer division for very small nums */
+               link_percentage = (link_percentage * bw_percent) / 100;
+               if (p->bwg_percent > 0 && link_percentage == 0)
+                       link_percentage = 1;
+
+               /* Save link_percentage for reference */
+               p->link_percent = (u8)link_percentage;
+
+               /* Calculate credit refill and save it */
+               credit_refill = link_percentage * MINIMUM_CREDIT_REFILL;
+               p->data_credits_refill = (u16)credit_refill;
+
+               /* Calculate maximum credit for the TC */
+               credit_max = (link_percentage * MAX_CREDIT) / 100;
+
+               /*
+                * Adjustment based on rule checking, if the percentage
+                * of a TC is too small, the maximum credit may not be
+                * enough to send out a jumbo frame in data plane arbitration.
+                */
+               if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_JUMBO))
+                       credit_max = MINIMUM_CREDIT_FOR_JUMBO;
+
+               if (direction == DCB_TX_CONFIG) {
+                       /*
+                        * Adjustment based on rule checking, if the
+                        * percentage of a TC is too small, the maximum
+                        * credit may not be enough to send out a TSO
+                        * packet in descriptor plane arbitration.
+                        */
+                       if (credit_max && (credit_max < MINIMUM_CREDIT_FOR_TSO))
+                               credit_max = MINIMUM_CREDIT_FOR_TSO;
+
+                       dcb_config->tc_config[i].desc_credits_max =
+                          (u16)credit_max;
+               }
+
+               p->data_credits_max = (u16)credit_max;
+       }
+
+out:
+       return ret_val;
+}
+
+/**
+ * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
+ * @hw: pointer to hardware structure
+ * @stats: pointer to statistics structure
+ * @tc_count:  Number of elements in bwg_array.
+ *
+ * This function returns the status data for each of the Traffic Classes in 
use.
+ */
+s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
+                           u8 tc_count)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
+ * @hw: pointer to hardware structure
+ * @stats: pointer to statistics structure
+ * @tc_count:  Number of elements in bwg_array.
+ *
+ * This function returns the CBFC status data for each of the Traffic Classes.
+ */
+s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
+                            u8 tc_count)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_config_rx_arbiter - Config Rx arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Rx Data Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw,
+                                struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_config_tx_desc_arbiter - Config Tx Desc arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Tx Descriptor Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw,
+                                     struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_config_tx_data_arbiter - Config Tx data arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Tx Data Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw,
+                                     struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_config_pfc - Config priority flow control
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Priority Flow Control for each traffic class.
+ */
+s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw,
+                         struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_config_pfc_82598(hw, dcb_config);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_config_tc_stats - Config traffic class statistics
+ * @hw: pointer to hardware structure
+ *
+ * Configure queue statistics registers, all queues belonging to same traffic
+ * class uses a single set of queue statistics counters.
+ */
+s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_config_tc_stats_82598(hw);
+       return ret;
+}
+
+/**
+ * ixgbe_dcb_hw_config - Config and enable DCB
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure dcb settings and enable dcb mode.
+ */
+s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
+                        struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret = 0;
+       if (hw->mac.type == ixgbe_mac_82598EB)
+               ret = ixgbe_dcb_hw_config_82598(hw, dcb_config);
+       return ret;
+}
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_dcb.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_dcb.h     Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,167 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _DCB_CONFIG_H_
+#define _DCB_CONFIG_H_
+
+#include "ixgbe_type.h"
+
+/* DCB data structures */
+
+#define IXGBE_MAX_PACKET_BUFFERS 8
+#define MAX_USER_PRIORITY        8
+#define MAX_TRAFFIC_CLASS        8
+#define MAX_BW_GROUP             8
+#define BW_PERCENT               100
+
+#define DCB_TX_CONFIG            0
+#define DCB_RX_CONFIG            1
+
+/* DCB error Codes */
+#define DCB_SUCCESS              0
+#define DCB_ERR_CONFIG           -1
+#define DCB_ERR_PARAM            -2
+
+/* Transmit and receive Errors */
+/* Error in bandwidth group allocation */
+#define DCB_ERR_BW_GROUP        -3
+/* Error in traffic class bandwidth allocation */
+#define DCB_ERR_TC_BW           -4
+/* Traffic class has both link strict and group strict enabled */
+#define DCB_ERR_LS_GS           -5
+/* Link strict traffic class has non zero bandwidth */
+#define DCB_ERR_LS_BW_NONZERO   -6
+/* Link strict bandwidth group has non zero bandwidth */
+#define DCB_ERR_LS_BWG_NONZERO  -7
+/*  Traffic class has zero bandwidth */
+#define DCB_ERR_TC_BW_ZERO      -8
+
+#define DCB_NOT_IMPLEMENTED      0x7FFFFFFF
+
+struct dcb_pfc_tc_debug {
+       u8  tc;
+       u8  pause_status;
+       u64 pause_quanta;
+};
+
+enum strict_prio_type {
+       prio_none = 0,
+       prio_group,
+       prio_link
+};
+
+/* Traffic class bandwidth allocation per direction */
+struct tc_bw_alloc {
+       u8 bwg_id;                /* Bandwidth Group (BWG) ID */
+       u8 bwg_percent;           /* % of BWG's bandwidth */
+       u8 link_percent;          /* % of link bandwidth */
+       u8 up_to_tc_bitmap;       /* User Priority to Traffic Class mapping */
+       u16 data_credits_refill;  /* Credit refill amount in 64B granularity */
+       u16 data_credits_max;     /* Max credits for a configured packet buffer
+                                  * in 64B granularity.*/
+       enum strict_prio_type prio_type; /* Link or Group Strict Priority */
+};
+
+enum dcb_pfc_type {
+       pfc_disabled = 0,
+       pfc_enabled_full,
+       pfc_enabled_tx,
+       pfc_enabled_rx
+};
+
+/* Traffic class configuration */
+struct tc_configuration {
+       struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
+       enum dcb_pfc_type  dcb_pfc; /* Class based flow control setting */
+
+       u16 desc_credits_max; /* For Tx Descriptor arbitration */
+       u8 tc; /* Traffic class (TC) */
+};
+
+enum dcb_rx_pba_cfg {
+       pba_equal,     /* PBA[0-7] each use 64KB FIFO */
+       pba_80_48      /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
+};
+
+
+struct ixgbe_dcb_config {
+       struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
+       u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
+       bool pfc_mode_enable;
+       bool  round_robin_enable;
+
+       enum dcb_rx_pba_cfg rx_pba_cfg;
+
+       u32  dcb_cfg_version; /* Not used...OS-specific? */
+       u32  link_speed; /* For bandwidth allocation validation purpose */
+};
+
+/* DCB driver APIs */
+
+/* DCB rule checking function.*/
+s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *config);
+
+/* DCB credits calculation */
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *config,
+                                   u8 direction);
+
+/* DCB PFC functions */
+s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw,
+                         struct ixgbe_dcb_config *dcb_config);
+s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
+                            u8 tc_count);
+
+/* DCB traffic class stats */
+s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
+s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
+                           u8 tc_count);
+
+/* DCB config arbiters */
+s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *hw,
+                                     struct ixgbe_dcb_config *dcb_config);
+s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *hw,
+                                     struct ixgbe_dcb_config *dcb_config);
+s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *hw,
+                                struct ixgbe_dcb_config *dcb_config);
+
+/* DCB hw initialization */
+s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, struct ixgbe_dcb_config *config);
+
+
+/* DCB definitions for credit calculation */
+#define MAX_CREDIT_REFILL       511  /* 0x1FF * 64B = 32704B */
+#define MINIMUM_CREDIT_REFILL   5    /* 5*64B = 320B */
+#define MINIMUM_CREDIT_FOR_JUMBO 145  /* 145 = UpperBound((9*1024+54)/64B)
+                                       * for 9KB jumbo frame */
+#define DCB_MAX_TSO_SIZE        32*1024 /* MAX TSO packet size supported
+                                         * in DCB mode */
+#define MINIMUM_CREDIT_FOR_TSO  (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO
+                                                           * packet */
+#define MAX_CREDIT              4095 /* Maximum credit supported:
+                                      * 256KB * 1204 / 64B */
+
+#endif /* _DCB_CONFIG_H */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_dcb_82598.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c       Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,413 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+
+#include "ixgbe_type.h"
+#include "ixgbe_dcb.h"
+#include "ixgbe_dcb_82598.h"
+
+/**
+ * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
+ * @hw: pointer to hardware structure
+ * @stats: pointer to statistics structure
+ * @tc_count:  Number of elements in bwg_array.
+ *
+ * This function returns the status data for each of the Traffic Classes in 
use.
+ */
+s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
+                                 struct ixgbe_hw_stats *stats,
+                                 u8 tc_count)
+{
+       int tc;
+
+       if (tc_count > MAX_TRAFFIC_CLASS)
+               return DCB_ERR_PARAM;
+       /* Statistics pertaining to each traffic class */
+       for (tc = 0; tc < tc_count; tc++) {
+               /* Transmitted Packets */
+               stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
+               /* Transmitted Bytes */
+               stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
+               /* Received Packets */
+               stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
+               /* Received Bytes */
+               stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
+
+#if 0
+               /* Can we get rid of these??  Consequently, getting rid
+                * of the tc_stats structure.
+                */
+               tc_stats_array[up]->in_overflow_discards = 0;
+               tc_stats_array[up]->out_overflow_discards = 0;
+#endif
+       }
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
+ * @hw: pointer to hardware structure
+ * @stats: pointer to statistics structure
+ * @tc_count:  Number of elements in bwg_array.
+ *
+ * This function returns the CBFC status data for each of the Traffic Classes.
+ */
+s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
+                                  struct ixgbe_hw_stats *stats,
+                                  u8 tc_count)
+{
+       int tc;
+
+       if (tc_count > MAX_TRAFFIC_CLASS)
+               return DCB_ERR_PARAM;
+       for (tc = 0; tc < tc_count; tc++) {
+               /* Priority XOFF Transmitted */
+               stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
+               /* Priority XOFF Received */
+               stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
+       }
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_config_packet_buffers_82598 - Configure packet buffers
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure packet buffers for DCB mode.
+ */
+s32 ixgbe_dcb_config_packet_buffers_82598(struct ixgbe_hw *hw,
+                                          struct ixgbe_dcb_config *dcb_config)
+{
+       s32 ret_val = 0;
+       u32 value = IXGBE_RXPBSIZE_64KB;
+       u8  i = 0;
+
+       /* Setup Rx packet buffer sizes */
+       switch (dcb_config->rx_pba_cfg) {
+       case pba_80_48:
+               /* Setup the first four at 80KB */
+               value = IXGBE_RXPBSIZE_80KB;
+               for (; i < 4; i++)
+                       IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
+               /* Setup the last four at 48KB...don't re-init i */
+               value = IXGBE_RXPBSIZE_48KB;
+               /* Fall Through */
+       case pba_equal:
+       default:
+               for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
+                       IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value);
+
+               /* Setup Tx packet buffer sizes */
+               for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
+                       IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i),
+                                       IXGBE_TXPBSIZE_40KB);
+               }
+               break;
+       }
+
+       return ret_val;
+}
+
+/**
+ * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Rx Data Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
+                                      struct ixgbe_dcb_config *dcb_config)
+{
+       struct tc_bw_alloc    *p;
+       u32    reg           = 0;
+       u32    credit_refill = 0;
+       u32    credit_max    = 0;
+       u8     i             = 0;
+
+       reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
+       IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
+
+       reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
+       /* Enable Arbiter */
+       reg &= ~IXGBE_RMCS_ARBDIS;
+       /* Enable Receive Recycle within the BWG */
+       reg |= IXGBE_RMCS_RRM;
+       /* Enable Deficit Fixed Priority arbitration*/
+       reg |= IXGBE_RMCS_DFP;
+
+       IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
+
+       /* Configure traffic class credits and priority */
+       for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+               p = &dcb_config->tc_config[i].path[DCB_RX_CONFIG];
+               credit_refill = p->data_credits_refill;
+               credit_max    = p->data_credits_max;
+
+               reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
+
+               if (p->prio_type == prio_link)
+                       reg |= IXGBE_RT2CR_LSP;
+
+               IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
+       }
+
+       reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
+       reg |= IXGBE_RDRXCTL_RDMTS_1_2;
+       reg |= IXGBE_RDRXCTL_MPBEN;
+       reg |= IXGBE_RDRXCTL_MCEN;
+       IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
+
+       reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
+       /* Make sure there is enough descriptors before arbitration */
+       reg &= ~IXGBE_RXCTRL_DMBYPS;
+       IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Tx Descriptor Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
+                                           struct ixgbe_dcb_config *dcb_config)
+{
+       struct tc_bw_alloc *p;
+       u32    reg, max_credits;
+       u8     i;
+
+       reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
+
+       /* Enable arbiter */
+       reg &= ~IXGBE_DPMCS_ARBDIS;
+       if (!(dcb_config->round_robin_enable)) {
+               /* Enable DFP and Recycle mode */
+               reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
+       }
+       reg |= IXGBE_DPMCS_TSOEF;
+       /* Configure Max TSO packet size 34KB including payload and headers */
+       reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
+
+       IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
+
+       /* Configure traffic class credits and priority */
+       for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+               p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
+               max_credits = dcb_config->tc_config[i].desc_credits_max;
+               reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
+               reg |= p->data_credits_refill;
+               reg |= (u32)(p->bwg_id) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
+
+               if (p->prio_type == prio_group)
+                       reg |= IXGBE_TDTQ2TCCR_GSP;
+
+               if (p->prio_type == prio_link)
+                       reg |= IXGBE_TDTQ2TCCR_LSP;
+
+               IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
+       }
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Tx Data Arbiter and credits for each traffic class.
+ */
+s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
+                                           struct ixgbe_dcb_config *dcb_config)
+{
+       struct tc_bw_alloc *p;
+       u32 reg;
+       u8 i;
+
+       reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
+       /* Enable Data Plane Arbiter */
+       reg &= ~IXGBE_PDPMCS_ARBDIS;
+       /* Enable DFP and Transmit Recycle Mode */
+       reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
+
+       IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
+
+       /* Configure traffic class credits and priority */
+       for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+               p = &dcb_config->tc_config[i].path[DCB_TX_CONFIG];
+               reg = p->data_credits_refill;
+               reg |= (u32)(p->data_credits_max) << IXGBE_TDPT2TCCR_MCL_SHIFT;
+               reg |= (u32)(p->bwg_id) << IXGBE_TDPT2TCCR_BWG_SHIFT;
+
+               if (p->prio_type == prio_group)
+                       reg |= IXGBE_TDPT2TCCR_GSP;
+
+               if (p->prio_type == prio_link)
+                       reg |= IXGBE_TDPT2TCCR_LSP;
+
+               IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
+       }
+
+       /* Enable Tx packet buffer division */
+       reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
+       reg |= IXGBE_DTXCTL_ENDBUBD;
+       IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_config_pfc_82598 - Config priority flow control
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure Priority Flow Control for each traffic class.
+ */
+s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
+                               struct ixgbe_dcb_config *dcb_config)
+{
+       u32 reg, rx_pba_size;
+       u8  i;
+
+       /* Enable Transmit Priority Flow Control */
+       reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
+       reg &= ~IXGBE_RMCS_TFCE_802_3X;
+       /* correct the reporting of our flow control status */
+       hw->fc.current_mode = ixgbe_fc_none;
+       reg |= IXGBE_RMCS_TFCE_PRIORITY;
+       IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
+
+       /* Enable Receive Priority Flow Control */
+       reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+       reg &= ~IXGBE_FCTRL_RFCE;
+       reg |= IXGBE_FCTRL_RPFCE;
+       IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
+
+       /*
+        * Configure flow control thresholds and enable priority flow control
+        * for each traffic class.
+        */
+       for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
+               if (dcb_config->rx_pba_cfg == pba_equal) {
+                       rx_pba_size = IXGBE_RXPBSIZE_64KB;
+               } else {
+                       rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
+                                             : IXGBE_RXPBSIZE_48KB;
+               }
+
+               reg = ((rx_pba_size >> 5) &  0xFFF0);
+               if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
+                   dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                       reg |= IXGBE_FCRTL_XONE;
+
+               IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
+
+               reg = ((rx_pba_size >> 2) & 0xFFF0);
+               if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
+                   dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
+                       reg |= IXGBE_FCRTH_FCEN;
+
+               IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
+       }
+
+       /* Configure pause time */
+       for (i = 0; i < (MAX_TRAFFIC_CLASS >> 1); i++)
+               IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), 0x68006800);
+
+       /* Configure flow control refresh threshold value */
+       IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
+ * @hw: pointer to hardware structure
+ *
+ * Configure queue statistics registers, all queues belonging to same traffic
+ * class uses a single set of queue statistics counters.
+ */
+s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
+{
+       u32 reg = 0;
+       u8  i   = 0;
+       u8  j   = 0;
+
+       /* Receive Queues stats setting -  8 queues per statistics reg */
+       for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
+               reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
+               reg |= ((0x1010101) * j);
+               IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
+               reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
+               reg |= ((0x1010101) * j);
+               IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
+       }
+       /* Transmit Queues stats setting -  4 queues per statistics reg*/
+       for (i = 0; i < 8; i++) {
+               reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
+               reg |= ((0x1010101) * i);
+               IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
+       }
+
+       return 0;
+}
+
+/**
+ * ixgbe_dcb_hw_config_82598 - Config and enable DCB
+ * @hw: pointer to hardware structure
+ * @dcb_config: pointer to ixgbe_dcb_config structure
+ *
+ * Configure dcb settings and enable dcb mode.
+ */
+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
+                              struct ixgbe_dcb_config *dcb_config)
+{
+       u32  pap = 0;
+
+       ixgbe_dcb_config_packet_buffers_82598(hw, dcb_config);
+       ixgbe_dcb_config_rx_arbiter_82598(hw, dcb_config);
+       ixgbe_dcb_config_tx_desc_arbiter_82598(hw, dcb_config);
+       ixgbe_dcb_config_tx_data_arbiter_82598(hw, dcb_config);
+       ixgbe_dcb_config_pfc_82598(hw, dcb_config);
+       ixgbe_dcb_config_tc_stats_82598(hw);
+
+       /* TODO: For DCB SV purpose only,
+        * remove it before product release */
+       if (dcb_config->link_speed > 0 && dcb_config->link_speed <= 9) {
+               pap = IXGBE_READ_REG(hw, IXGBE_PAP);
+               pap |= (dcb_config->link_speed << 16);
+               IXGBE_WRITE_REG(hw, IXGBE_PAP, pap);
+       }
+
+       return 0;
+}
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_dcb_82598.h
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.h       Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,99 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _DCB_82598_CONFIG_H_
+#define _DCB_82598_CONFIG_H_
+
+/* DCB register definitions */
+
+#define IXGBE_DPMCS_MTSOS_SHIFT 16
+#define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin,
+                                            * 1 DFP - Deficit Fixed Priority */
+#define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
+#define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
+#define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
+
+#define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
+
+#define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
+#define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
+
+#define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
+                                            * buffers enable */
+#define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
+                                            * (RSS) enable */
+
+#define IXGBE_TDTQ2TCCR_MCL_SHIFT   12
+#define IXGBE_TDTQ2TCCR_BWG_SHIFT   9
+#define IXGBE_TDTQ2TCCR_GSP     0x40000000
+#define IXGBE_TDTQ2TCCR_LSP     0x80000000
+
+#define IXGBE_TDPT2TCCR_MCL_SHIFT   12
+#define IXGBE_TDPT2TCCR_BWG_SHIFT   9
+#define IXGBE_TDPT2TCCR_GSP     0x40000000
+#define IXGBE_TDPT2TCCR_LSP     0x80000000
+
+#define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin,
+                                            * 1 DFP - Deficit Fixed Priority */
+#define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
+#define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
+
+#define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
+
+#define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
+#define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
+#define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
+#define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
+
+/* DCB hardware-specific driver APIs */
+
+/* DCB PFC functions */
+s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
+                               struct ixgbe_dcb_config *dcb_config);
+s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
+                                  struct ixgbe_hw_stats *stats,
+                                  u8 tc_count);
+
+/* DCB traffic class stats */
+s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw);
+s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
+                                 struct ixgbe_hw_stats *stats,
+                                 u8 tc_count);
+
+/* DCB config arbiters */
+s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
+                                           struct ixgbe_dcb_config 
*dcb_config);
+s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
+                                           struct ixgbe_dcb_config 
*dcb_config);
+s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
+                                      struct ixgbe_dcb_config *dcb_config);
+
+/* DCB hw initialization */
+s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw,
+                              struct ixgbe_dcb_config *config);
+
+#endif /* _DCB_82598_CONFIG_H */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_ethtool.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,1941 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+/* ethtool support for ixgbe */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#ifdef SIOCETHTOOL
+#include <asm/uaccess.h>
+
+#include "ixgbe.h"
+
+#ifndef ETH_GSTRING_LEN
+#define ETH_GSTRING_LEN 32
+#endif
+
+#define IXGBE_ALL_RAR_ENTRIES 16
+
+#ifdef ETHTOOL_OPS_COMPAT
+#include "kcompat_ethtool.c"
+#endif
+#ifdef ETHTOOL_GSTATS
+struct ixgbe_stats {
+       char stat_string[ETH_GSTRING_LEN];
+       int sizeof_stat;
+       int stat_offset;
+};
+
+#define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
+                     offsetof(struct ixgbe_adapter, m)
+static struct ixgbe_stats ixgbe_gstrings_stats[] = {
+       {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
+       {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
+       {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
+       {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
+       {"lsc_int", IXGBE_STAT(lsc_int)},
+       {"tx_busy", IXGBE_STAT(tx_busy)},
+       {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
+       {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
+       {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
+       {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
+#ifndef CONFIG_IXGBE_NAPI
+       {"rx_dropped_backlog", IXGBE_STAT(rx_dropped_backlog)},
+#endif
+       {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
+       {"multicast", IXGBE_STAT(net_stats.multicast)},
+       {"broadcast", IXGBE_STAT(stats.bprc)},
+       {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
+       {"collisions", IXGBE_STAT(net_stats.collisions)},
+       {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
+       {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
+       {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
+       {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
+       {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
+       {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
+       {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
+       {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
+       {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
+       {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
+       {"tx_restart_queue", IXGBE_STAT(restart_queue)},
+       {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
+       {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
+#ifdef NETIF_F_TSO
+       {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
+#ifdef NETIF_F_TSO6
+       {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
+#endif
+#endif
+       {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
+       {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
+       {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
+       {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
+       {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
+       {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
+       {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
+       {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
+#ifndef IXGBE_NO_LLI
+       {"low_latency_interrupt", IXGBE_STAT(lli_int)},
+#endif
+       {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
+       {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
+#ifndef IXGBE_NO_LRO
+       {"lro_aggregated", IXGBE_STAT(lro_data.stats.coal)},
+       {"lro_flushed", IXGBE_STAT(lro_data.stats.flushed)},
+#endif /* IXGBE_NO_LRO */
+#ifndef IXGBE_NO_INET_LRO
+       {"lro_aggregated", IXGBE_STAT(lro_aggregated)},
+       {"lro_flushed", IXGBE_STAT(lro_flushed)},
+#endif
+};
+
+#define IXGBE_QUEUE_STATS_LEN \
+           ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
+             ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
+             (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
+#define IXGBE_PB_STATS_LEN ( \
+               (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
+                IXGBE_FLAG_DCB_ENABLED) ? \
+                (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
+                 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
+                 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
+                 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
+                / sizeof(u64) : 0)
+#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_PB_STATS_LEN + 
IXGBE_QUEUE_STATS_LEN)
+#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
+#endif /* ETHTOOL_GSTATS */
+#ifdef ETHTOOL_TEST
+static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
+       "Register test  (offline)", "Eeprom test    (offline)",
+       "Interrupt test (offline)", "Loopback test  (offline)",
+       "Link test   (on/offline)"
+};
+#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
+#endif /* ETHTOOL_TEST */
+
+static int ixgbe_get_settings(struct net_device *netdev,
+                              struct ethtool_cmd *ecmd)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 link_speed = 0;
+       bool link_up;
+
+       ecmd->supported = SUPPORTED_10000baseT_Full;
+       ecmd->autoneg = AUTONEG_ENABLE;
+       ecmd->transceiver = XCVR_EXTERNAL;
+       if (hw->phy.media_type == ixgbe_media_type_copper) {
+               ecmd->supported |= (SUPPORTED_1000baseT_Full |
+                                   SUPPORTED_TP | SUPPORTED_Autoneg);
+
+               ecmd->advertising = (ADVERTISED_TP | ADVERTISED_Autoneg);
+               if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
+                       ecmd->advertising |= ADVERTISED_10000baseT_Full;
+               if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
+                       ecmd->advertising |= ADVERTISED_1000baseT_Full;
+
+               ecmd->port = PORT_TP;
+       } else {
+               ecmd->supported |= SUPPORTED_FIBRE;
+               ecmd->advertising = (ADVERTISED_10000baseT_Full |
+                                    ADVERTISED_FIBRE);
+               ecmd->port = PORT_FIBRE;
+               ecmd->autoneg = AUTONEG_DISABLE;
+       }
+
+       if (!in_interrupt()) {
+               hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
+       } else {
+               /*
+                * this case is a special workaround for RHEL5 bonding
+                * that calls this routine from interrupt context
+                */
+               link_speed = adapter->link_speed;
+               link_up = adapter->link_up;
+       }
+
+       if (link_up) {
+               ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
+                              SPEED_10000 : SPEED_1000;
+               ecmd->duplex = DUPLEX_FULL;
+       } else {
+               ecmd->speed = -1;
+               ecmd->duplex = -1;
+       }
+
+       return 0;
+}
+
+static int ixgbe_set_settings(struct net_device *netdev,
+                              struct ethtool_cmd *ecmd)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 advertised, old;
+       s32 err;
+
+       switch (hw->phy.media_type) {
+       case ixgbe_media_type_fiber:
+               if ((ecmd->autoneg == AUTONEG_ENABLE) ||
+                   (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
+                       return -EINVAL;
+               /* in this case we currently only support 10Gb/FULL */
+               break;
+       case ixgbe_media_type_copper:
+               /* 10000/copper and 1000/copper must autoneg
+                * this function does not support any duplex forcing, but can
+                * limit the advertising of the adapter to only 10000 or 1000 */
+               if (ecmd->autoneg == AUTONEG_DISABLE)
+                       return -EINVAL;
+
+               old = hw->phy.autoneg_advertised;
+               advertised = 0;
+               if (ecmd->advertising & ADVERTISED_10000baseT_Full)
+                       advertised |= IXGBE_LINK_SPEED_10GB_FULL;
+
+               if (ecmd->advertising & ADVERTISED_1000baseT_Full)
+                       advertised |= IXGBE_LINK_SPEED_1GB_FULL;
+
+               if (old == advertised)
+                       break;
+               /* this sets the link speed and restarts auto-neg */
+               err = hw->mac.ops.setup_link_speed(hw, advertised, true, true);
+               if (err) {
+                       DPRINTK(PROBE, INFO,
+                               "setup link failed with code %d\n", err);
+                       hw->mac.ops.setup_link_speed(hw, old, true, true);
+               }
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+static void ixgbe_get_pauseparam(struct net_device *netdev,
+                                 struct ethtool_pauseparam *pause)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       pause->autoneg = (hw->fc.current_mode == ixgbe_fc_full ? 1 : 0);
+
+       if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
+               pause->rx_pause = 1;
+       } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
+               pause->tx_pause = 1;
+       } else if (hw->fc.current_mode == ixgbe_fc_full) {
+               pause->rx_pause = 1;
+               pause->tx_pause = 1;
+       }
+}
+
+static int ixgbe_set_pauseparam(struct net_device *netdev,
+                                struct ethtool_pauseparam *pause)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       if ((pause->autoneg == AUTONEG_ENABLE) ||
+           (pause->rx_pause && pause->tx_pause))
+               hw->fc.current_mode = ixgbe_fc_full;
+       else if (pause->rx_pause && !pause->tx_pause)
+               hw->fc.current_mode = ixgbe_fc_rx_pause;
+       else if (!pause->rx_pause && pause->tx_pause)
+               hw->fc.current_mode = ixgbe_fc_tx_pause;
+       else if (!pause->rx_pause && !pause->tx_pause)
+               hw->fc.current_mode = ixgbe_fc_none;
+       else
+               return -EINVAL;
+
+       hw->fc.requested_mode = hw->fc.current_mode;
+
+       if (netif_running(netdev))
+               ixgbe_reinit_locked(adapter);
+       else
+               ixgbe_reset(adapter);
+
+       return 0;
+}
+
+static u32 ixgbe_get_rx_csum(struct net_device *netdev)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
+}
+
+static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       if (data)
+               adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
+       else
+               adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
+
+       if (netif_running(netdev))
+               ixgbe_reinit_locked(adapter);
+       else
+               ixgbe_reset(adapter);
+
+       return 0;
+}
+
+static u32 ixgbe_get_tx_csum(struct net_device *netdev)
+{
+       return (netdev->features & NETIF_F_IP_CSUM) != 0;
+}
+
+static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
+{
+       if (data)
+#ifdef NETIF_F_IPV6_CSUM
+               netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+       else
+               netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+#else
+               netdev->features |= NETIF_F_IP_CSUM;
+       else
+               netdev->features &= ~NETIF_F_IP_CSUM;
+#endif
+
+       return 0;
+}
+
+#ifdef NETIF_F_TSO
+static int ixgbe_set_tso(struct net_device *netdev, u32 data)
+{
+#ifndef HAVE_NETDEV_VLAN_FEATURES
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+#endif /* HAVE_NETDEV_VLAN_FEATURES */
+       if (data) {
+               netdev->features |= NETIF_F_TSO;
+#ifdef NETIF_F_TSO6
+               netdev->features |= NETIF_F_TSO6;
+#endif
+       } else {
+               netif_tx_stop_all_queues(netdev);
+               netdev->features &= ~NETIF_F_TSO;
+#ifdef NETIF_F_TSO6
+               netdev->features &= ~NETIF_F_TSO6;
+#endif
+#ifndef HAVE_NETDEV_VLAN_FEATURES
+#ifdef NETIF_F_HW_VLAN_TX
+               /* disable TSO on all VLANs if they're present */
+               if (adapter->vlgrp) {
+                       int i;
+                       struct net_device *v_netdev;
+                       for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+                               v_netdev =
+                                      vlan_group_get_device(adapter->vlgrp, i);
+                               if (v_netdev) {
+                                       v_netdev->features &= ~NETIF_F_TSO;
+#ifdef NETIF_F_TSO6
+                                       v_netdev->features &= ~NETIF_F_TSO6;
+#endif
+                                       vlan_group_set_device(adapter->vlgrp, i,
+                                                             v_netdev);
+                               }
+                       }
+               }
+#endif
+#endif /* HAVE_NETDEV_VLAN_FEATURES */
+               netif_tx_start_all_queues(netdev);
+       }
+       return 0;
+}
+#endif /* NETIF_F_TSO */
+
+static u32 ixgbe_get_msglevel(struct net_device *netdev)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       return adapter->msg_enable;
+}
+
+static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       adapter->msg_enable = data;
+}
+
+static int ixgbe_get_regs_len(struct net_device *netdev)
+{
+#define IXGBE_REGS_LEN  1128
+       return IXGBE_REGS_LEN * sizeof(u32);
+}
+
+#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
+
+static void ixgbe_get_regs(struct net_device *netdev, struct ethtool_regs 
*regs,
+                           void *p)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 *regs_buff = p;
+       u8 i;
+
+       memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
+
+       regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
+
+       /* General Registers */
+       regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
+       regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
+       regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
+       regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
+       regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
+       regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
+       regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
+       regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
+
+       /* NVM Register */
+       regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
+       regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
+       regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
+       regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
+       regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
+       regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
+       regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
+       regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
+       regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
+       regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
+
+       /* Interrupt */
+       /* don't read EICR because it can clear interrupt causes, instead
+        * read EICS which is a shadow but doesn't clear EICR */
+       regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
+       regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
+       regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
+       regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
+       regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
+       regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
+       regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
+       regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
+       regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
+       regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
+       regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
+       regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
+
+       /* Flow Control */
+       regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
+       regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
+       regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
+       regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
+       regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
+       for (i = 0; i < 8; i++)
+               regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
+       regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
+       regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
+
+       /* Receive DMA */
+       for (i = 0; i < 64; i++)
+               regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
+       for (i = 0; i < 64; i++)
+               regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
+       for (i = 0; i < 64; i++)
+               regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
+       for (i = 0; i < 64; i++)
+               regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
+       for (i = 0; i < 64; i++)
+               regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
+       for (i = 0; i < 64; i++)
+               regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
+       for (i = 0; i < 16; i++)
+               regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
+       for (i = 0; i < 16; i++)
+               regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
+       regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
+       for (i = 0; i < 8; i++)
+               regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
+       regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
+       regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
+
+       /* Receive */
+       regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
+       regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
+       for (i = 0; i < 16; i++)
+               regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
+       for (i = 0; i < 16; i++)
+               regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
+       regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
+       regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
+       regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
+       regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
+       regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
+       regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
+       for (i = 0; i < 8; i++)
+               regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
+       regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
+
+       /* Transmit */
+       for (i = 0; i < 32; i++)
+               regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
+       for (i = 0; i < 32; i++)
+               regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
+       regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
+       for (i = 0; i < 16; i++)
+               regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
+       regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
+       for (i = 0; i < 8; i++)
+               regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
+       regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
+
+       /* Wake Up */
+       regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
+       regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
+       regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
+       regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
+       regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
+       regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
+       regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
+       regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
+       regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
+
+       /* DCB */
+       regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
+       regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
+       regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
+       regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
+       for (i = 0; i < 8; i++)
+               regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
+       for (i = 0; i < 8; i++)
+               regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
+
+       /* Statistics */
+       regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
+       regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
+       regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
+       regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
+       for (i = 0; i < 8; i++)
+               regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
+       regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
+       regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
+       regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
+       regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
+       regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
+       regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
+       regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
+       for (i = 0; i < 8; i++)
+               regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
+       for (i = 0; i < 8; i++)
+               regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
+       for (i = 0; i < 8; i++)
+               regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
+       for (i = 0; i < 8; i++)
+               regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
+       regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
+       regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
+       regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
+       regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
+       regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
+       regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
+       regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
+       regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
+       regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
+       regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
+       regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
+       regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
+       for (i = 0; i < 8; i++)
+               regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
+       regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
+       regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
+       regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
+       regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
+       regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
+       regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
+       regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
+       regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
+       regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
+       regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
+       regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
+       regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
+       regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
+       regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
+       regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
+       regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
+       regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
+       regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
+       regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
+       for (i = 0; i < 16; i++)
+               regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
+       for (i = 0; i < 16; i++)
+               regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
+       for (i = 0; i < 16; i++)
+               regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
+       for (i = 0; i < 16; i++)
+               regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
+
+       /* MAC */
+       regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
+       regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
+       regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
+       regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
+       regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
+       regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
+       regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
+       regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
+       regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
+       regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
+       regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
+       regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
+       regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
+       regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
+       regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
+       regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
+       regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
+       regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
+       regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
+       regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
+       regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
+       regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
+       regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
+       regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
+       regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
+       regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
+       regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+       regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
+       regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
+       regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
+       regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
+       regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
+       regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
+
+       /* Diagnostic */
+       regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
+       for (i = 0; i < 8; i++)
+               regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
+       regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
+       for (i = 0; i < 4; i++)
+               regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
+       regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
+       regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
+       for (i = 0; i < 8; i++)
+               regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
+       regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
+       for (i = 0; i < 4; i++)
+               regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
+       regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
+       regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
+       regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
+       regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
+       regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
+       regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
+       regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
+       regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
+       regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
+       regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
+       regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
+       for (i = 0; i < 8; i++)
+               regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
+       regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
+       regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
+       regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
+       regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
+       regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
+       regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
+       regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
+       regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
+       regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
+}
+
+static int ixgbe_get_eeprom_len(struct net_device *netdev)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       return adapter->hw.eeprom.word_size * 2;
+}
+
+static int ixgbe_get_eeprom(struct net_device *netdev,
+                            struct ethtool_eeprom *eeprom, u8 *bytes)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u16 *eeprom_buff;
+       int first_word, last_word, eeprom_len;
+       int ret_val = 0;
+       u16 i;
+
+       if (eeprom->len == 0)
+               return -EINVAL;
+
+       eeprom->magic = hw->vendor_id | (hw->device_id << 16);
+
+       first_word = eeprom->offset >> 1;
+       last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+       eeprom_len = last_word - first_word + 1;
+
+       eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
+       if (!eeprom_buff)
+               return -ENOMEM;
+
+       for (i = 0; i < eeprom_len; i++) {
+               if ((ret_val = ixgbe_read_eeprom(hw, first_word + i,
+                                                &eeprom_buff[i])))
+                       break;
+       }
+
+       /* Device's eeprom is always little-endian, word addressable */
+       for (i = 0; i < eeprom_len; i++)
+               le16_to_cpus(&eeprom_buff[i]);
+
+       memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
+       kfree(eeprom_buff);
+
+       return ret_val;
+}
+
+static int ixgbe_set_eeprom(struct net_device *netdev,
+                            struct ethtool_eeprom *eeprom, u8 *bytes)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u16 *eeprom_buff;
+       void *ptr;
+       int max_len, first_word, last_word, ret_val = 0;
+       u16 i;
+
+       if (eeprom->len == 0)
+               return -EOPNOTSUPP;
+
+       if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
+               return -EFAULT;
+
+       max_len = hw->eeprom.word_size * 2;
+
+       first_word = eeprom->offset >> 1;
+       last_word = (eeprom->offset + eeprom->len - 1) >> 1;
+       eeprom_buff = kmalloc(max_len, GFP_KERNEL);
+       if (!eeprom_buff)
+               return -ENOMEM;
+
+       ptr = (void *)eeprom_buff;
+
+       if (eeprom->offset & 1) {
+               /* need read/modify/write of first changed EEPROM word */
+               /* only the second byte of the word is being modified */
+               ret_val = ixgbe_read_eeprom(hw, first_word, &eeprom_buff[0]);
+               ptr++;
+       }
+       if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
+               /* need read/modify/write of last changed EEPROM word */
+               /* only the first byte of the word is being modified */
+               ret_val = ixgbe_read_eeprom(hw, last_word,
+                                 &eeprom_buff[last_word - first_word]);
+       }
+
+       /* Device's eeprom is always little-endian, word addressable */
+       for (i = 0; i < last_word - first_word + 1; i++)
+               le16_to_cpus(&eeprom_buff[i]);
+
+       memcpy(ptr, bytes, eeprom->len);
+
+       for (i = 0; i <= (last_word - first_word); i++)
+               ret_val |= ixgbe_write_eeprom(hw, first_word + i, 
eeprom_buff[i]);
+
+       /* Update the checksum */
+       ixgbe_update_eeprom_checksum(hw);
+
+       kfree(eeprom_buff);
+       return ret_val;
+}
+
+static void ixgbe_get_drvinfo(struct net_device *netdev,
+                              struct ethtool_drvinfo *drvinfo)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       strncpy(drvinfo->driver, ixgbe_driver_name, 32);
+       strncpy(drvinfo->version, ixgbe_driver_version, 32);
+       strncpy(drvinfo->fw_version, "N/A", 32);
+       strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+       drvinfo->n_stats = IXGBE_STATS_LEN;
+       drvinfo->testinfo_len = IXGBE_TEST_LEN;
+       drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
+}
+
+static void ixgbe_get_ringparam(struct net_device *netdev,
+                                struct ethtool_ringparam *ring)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_ring *tx_ring = adapter->tx_ring;
+       struct ixgbe_ring *rx_ring = adapter->rx_ring;
+
+       ring->rx_max_pending = IXGBE_MAX_RXD;
+       ring->tx_max_pending = IXGBE_MAX_TXD;
+       ring->rx_mini_max_pending = 0;
+       ring->rx_jumbo_max_pending = 0;
+       ring->rx_pending = rx_ring->count;
+       ring->tx_pending = tx_ring->count;
+       ring->rx_mini_pending = 0;
+       ring->rx_jumbo_pending = 0;
+}
+
+static int ixgbe_set_ringparam(struct net_device *netdev,
+                               struct ethtool_ringparam *ring)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_ring *temp_ring;
+       int i, err;
+       u32 new_rx_count, new_tx_count;
+
+       if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
+               return -EINVAL;
+
+       new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
+       new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
+       new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
+
+       new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
+       new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
+       new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
+
+       if ((new_tx_count == adapter->tx_ring->count) &&
+           (new_rx_count == adapter->rx_ring->count)) {
+               /* nothing to do */
+               return 0;
+       }
+
+       if (adapter->num_tx_queues > adapter->num_rx_queues)
+               temp_ring = vmalloc(adapter->num_tx_queues *
+                                   sizeof(struct ixgbe_ring));
+       else
+               temp_ring = vmalloc(adapter->num_rx_queues *
+                                   sizeof(struct ixgbe_ring));
+       if (!temp_ring)
+               return -ENOMEM;
+
+       while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
+               msleep(1);
+
+       if (netif_running(netdev))
+               ixgbe_down(adapter);
+
+       /*
+        * We can't just free everything and then setup again,
+        * because the ISRs in MSI-X mode get passed pointers
+        * to the tx and rx ring structs.
+        */
+       if (new_tx_count != adapter->tx_ring->count) {
+               memcpy(temp_ring, adapter->tx_ring,
+                      adapter->num_tx_queues * sizeof(struct ixgbe_ring));
+
+               for (i = 0; i < adapter->num_tx_queues; i++) {
+                       temp_ring[i].count = new_tx_count;
+                       err = ixgbe_setup_tx_resources(adapter, &temp_ring[i]);
+                       if (err) {
+                               while (i) {
+                                       i--;
+                                       ixgbe_free_tx_resources(adapter,
+                                                               &temp_ring[i]);
+                               }
+                               goto err_setup;
+                       }
+               }
+
+               for (i = 0; i < adapter->num_tx_queues; i++)
+                       ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
+
+               memcpy(adapter->tx_ring, temp_ring,
+                      adapter->num_tx_queues * sizeof(struct ixgbe_ring));
+
+               adapter->tx_ring_count = new_tx_count;
+       }
+
+       if (new_rx_count != adapter->rx_ring->count) {
+               memcpy(temp_ring, adapter->rx_ring,
+                      adapter->num_rx_queues * sizeof(struct ixgbe_ring));
+
+               for (i = 0; i < adapter->num_rx_queues; i++) {
+                       temp_ring[i].count = new_rx_count;
+                       err = ixgbe_setup_rx_resources(adapter, &temp_ring[i]);
+                       if (err) {
+                               while (i) {
+                                       i--;
+                                       ixgbe_free_rx_resources(adapter,
+                                                               &temp_ring[i]);
+                               }
+                               goto err_setup;
+                       }
+               }
+
+               for (i = 0; i < adapter->num_rx_queues; i++)
+                       ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
+
+               memcpy(adapter->rx_ring, temp_ring,
+                      adapter->num_rx_queues * sizeof(struct ixgbe_ring));
+
+               adapter->rx_ring_count = new_rx_count;
+       }
+
+       /* success! */
+       err = 0;
+err_setup:
+       if (netif_running(netdev))
+               ixgbe_up(adapter);
+
+       clear_bit(__IXGBE_RESETTING, &adapter->state);
+       return err;
+}
+
+static int ixgbe_get_stats_count(struct net_device *netdev)
+{
+       return IXGBE_STATS_LEN;
+}
+
+static void ixgbe_get_ethtool_stats(struct net_device *netdev,
+                                    struct ethtool_stats *stats, u64 *data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       u64 *queue_stat;
+       int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
+       int j, k;
+       int i;
+
+#ifndef IXGBE_NO_INET_LRO
+       unsigned int aggregated = 0, flushed = 0, no_desc = 0;
+
+       for (i = 0; i < adapter->num_rx_queues; i++) {
+               aggregated += adapter->rx_ring[i].lro_mgr.stats.aggregated;
+               flushed += adapter->rx_ring[i].lro_mgr.stats.flushed;
+               no_desc += adapter->rx_ring[i].lro_mgr.stats.no_desc;
+       }
+       adapter->lro_aggregated = aggregated;
+       adapter->lro_flushed = flushed;
+       adapter->lro_no_desc = no_desc;
+
+#endif
+       ixgbe_update_stats(adapter);
+       for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
+               char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
+               data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
+                          sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+       }
+       for (j = 0; j < adapter->num_tx_queues; j++) {
+               queue_stat = (u64 *)&adapter->tx_ring[j].stats;
+               for (k = 0; k < stat_count; k++)
+                       data[i + k] = queue_stat[k];
+               i += k;
+       }
+       for (j = 0; j < adapter->num_rx_queues; j++) {
+               queue_stat = (u64 *)&adapter->rx_ring[j].stats;
+               for (k = 0; k < stat_count; k++)
+                       data[i + k] = queue_stat[k];
+               i += k;
+       }
+       if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
+               for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
+                       data[i++] = adapter->stats.pxontxc[j];
+                       data[i++] = adapter->stats.pxofftxc[j];
+               }
+               for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
+                       data[i++] = adapter->stats.pxonrxc[j];
+                       data[i++] = adapter->stats.pxoffrxc[j];
+               }
+       }
+}
+
+static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
+                              u8 *data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       char *p = (char *)data;
+       int i;
+
+       switch (stringset) {
+       case ETH_SS_TEST:
+               memcpy(data, *ixgbe_gstrings_test,
+                      IXGBE_TEST_LEN * ETH_GSTRING_LEN);
+               break;
+       case ETH_SS_STATS:
+               for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
+                       memcpy(p, ixgbe_gstrings_stats[i].stat_string,
+                              ETH_GSTRING_LEN);
+                       p += ETH_GSTRING_LEN;
+               }
+               for (i = 0; i < adapter->num_tx_queues; i++) {
+                       sprintf(p, "tx_queue_%u_packets", i);
+                       p += ETH_GSTRING_LEN;
+                       sprintf(p, "tx_queue_%u_bytes", i);
+                       p += ETH_GSTRING_LEN;
+               }
+               for (i = 0; i < adapter->num_rx_queues; i++) {
+                       sprintf(p, "rx_queue_%u_packets", i);
+                       p += ETH_GSTRING_LEN;
+                       sprintf(p, "rx_queue_%u_bytes", i);
+                       p += ETH_GSTRING_LEN;
+               }
+               if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
+                       for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
+                               sprintf(p, "tx_pb_%u_pxon", i);
+                               p += ETH_GSTRING_LEN;
+                               sprintf(p, "tx_pb_%u_pxoff", i);
+                               p += ETH_GSTRING_LEN;
+                       }
+                       for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
+                               sprintf(p, "rx_pb_%u_pxon", i);
+                               p += ETH_GSTRING_LEN;
+                               sprintf(p, "rx_pb_%u_pxoff", i);
+                               p += ETH_GSTRING_LEN;
+                       }
+               }
+/*             BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
+               break;
+       }
+}
+
+static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       bool link_up;
+       u32 link_speed = 0;
+       *data = 0;
+
+       hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
+       if (link_up)
+               return *data;
+       else
+               *data = 1;
+       return *data;
+}
+
+/* ethtool register test data */
+struct ixgbe_reg_test {
+       u16 reg;
+       u8  array_len;
+       u8  test_type;
+       u32 mask;
+       u32 write;
+};
+
+/* In the hardware, registers are laid out either singly, in arrays
+ * spaced 0x40 bytes apart, or in contiguous tables.  We assume
+ * most tests take place on arrays or single registers (handled
+ * as a single-element array) and special-case the tables.
+ * Table tests are always pattern tests.
+ *
+ * We also make provision for some required setup steps by specifying
+ * registers to be written without any read-back testing.
+ */
+
+#define PATTERN_TEST   1
+#define SET_READ_TEST  2
+#define WRITE_NO_TEST  3
+#define TABLE32_TEST   4
+#define TABLE64_TEST_LO        5
+#define TABLE64_TEST_HI        6
+
+/* default register test */
+static struct ixgbe_reg_test reg_test_82598[] = {
+       { IXGBE_FCRTL(0),       1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
+       { IXGBE_FCRTH(0),       1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
+       { IXGBE_PFCTOP,         1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+       { IXGBE_VLNCTRL,        1, PATTERN_TEST, 0x00000000, 0x00000000 },
+       { IXGBE_RDBAL(0),       4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
+       { IXGBE_RDBAH(0),       4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+       { IXGBE_RDLEN(0),       4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
+       /* Enable all four RX queues before testing. */
+       { IXGBE_RXDCTL(0),      4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
+       /* RDH is read-only for 82598, only test RDT. */
+       { IXGBE_RDT(0),         4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
+       { IXGBE_RXDCTL(0),      4, WRITE_NO_TEST, 0, 0 },
+       { IXGBE_FCRTH(0),       1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
+       { IXGBE_FCTTV(0),       1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+       { IXGBE_TIPG,           1, PATTERN_TEST, 0x000000FF, 0x000000FF },
+       { IXGBE_TDBAL(0),       4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
+       { IXGBE_TDBAH(0),       4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+       { IXGBE_TDLEN(0),       4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
+       { IXGBE_RXCTRL,         1, SET_READ_TEST, 0x00000003, 0x00000003 },
+       { IXGBE_DTXCTL,         1, SET_READ_TEST, 0x00000005, 0x00000005 },
+       { IXGBE_RAL(0),         16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
+       { IXGBE_RAL(0),         16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
+       { IXGBE_MTA(0),         128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
+       { 0, 0, 0, 0 }
+};
+
+#define REG_PATTERN_TEST(R, M, W)                                             \
+{                                                                             \
+       u32 pat, val, before;                                                 \
+       const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
+       for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
+               before = readl(adapter->hw.hw_addr + R);                      \
+               writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
+               val = readl(adapter->hw.hw_addr + R);                         \
+               if (val != (_test[pat] & W & M)) {                            \
+                       DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
+                                         "0x%08X expected 0x%08X\n",         \
+                               R, val, (_test[pat] & W & M));                \
+                       *data = R;                                            \
+                       writel(before, adapter->hw.hw_addr + R);              \
+                       return 1;                                             \
+               }                                                             \
+               writel(before, adapter->hw.hw_addr + R);                      \
+       }                                                                     \
+}
+
+#define REG_SET_AND_CHECK(R, M, W)                                            \
+{                                                                             \
+       u32 val, before;                                                      \
+       before = readl(adapter->hw.hw_addr + R);                              \
+       writel((W & M), (adapter->hw.hw_addr + R));                           \
+       val = readl(adapter->hw.hw_addr + R);                                 \
+       if ((W & M) != (val & M)) {                                           \
+               DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
+                                "expected 0x%08X\n", R, (val & M), (W & M)); \
+               *data = R;                                                    \
+               writel(before, (adapter->hw.hw_addr + R));                    \
+               return 1;                                                     \
+       }                                                                     \
+       writel(before, (adapter->hw.hw_addr + R));                            \
+}
+
+static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
+{
+       struct ixgbe_reg_test *test;
+       u32 value, before, after;
+       u32 i, toggle;
+
+       toggle = 0x7FFFF3FF;
+       test = reg_test_82598;
+
+       /*
+        * Because the status register is such a special case,
+        * we handle it separately from the rest of the register
+        * tests.  Some bits are read-only, some toggle, and some
+        * are writeable on newer MACs.
+        */
+       before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
+       value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
+       after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
+       if (value != after) {
+               DPRINTK(DRV, ERR, "failed STATUS register test got: "
+                       "0x%08X expected: 0x%08X\n", after, value);
+               *data = 1;
+               return 1;
+       }
+       /* restore previous status */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
+
+       /*
+        * Perform the remainder of the register test, looping through
+        * the test table until we either fail or reach the null entry.
+        */
+       while (test->reg) {
+               for (i = 0; i < test->array_len; i++) {
+                       switch (test->test_type) {
+                       case PATTERN_TEST:
+                               REG_PATTERN_TEST(test->reg + (i * 0x40),
+                                               test->mask,
+                                               test->write);
+                               break;
+                       case SET_READ_TEST:
+                               REG_SET_AND_CHECK(test->reg + (i * 0x40),
+                                               test->mask,
+                                               test->write);
+                               break;
+                       case WRITE_NO_TEST:
+                               writel(test->write,
+                                      (adapter->hw.hw_addr + test->reg)
+                                      + (i * 0x40));
+                               break;
+                       case TABLE32_TEST:
+                               REG_PATTERN_TEST(test->reg + (i * 4),
+                                               test->mask,
+                                               test->write);
+                               break;
+                       case TABLE64_TEST_LO:
+                               REG_PATTERN_TEST(test->reg + (i * 8),
+                                               test->mask,
+                                               test->write);
+                               break;
+                       case TABLE64_TEST_HI:
+                               REG_PATTERN_TEST((test->reg + 4) + (i * 8),
+                                               test->mask,
+                                               test->write);
+                               break;
+                       }
+               }
+               test++;
+       }
+
+       *data = 0;
+       return 0;
+}
+
+static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
+{
+       if (ixgbe_validate_eeprom_checksum(&adapter->hw, NULL))
+               *data = 1;
+       else
+               *data = 0;
+       return *data;
+}
+
+static irqreturn_t ixgbe_test_intr(int irq, void *data)
+{
+       struct net_device *netdev = (struct net_device *) data;
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
+
+       return IRQ_HANDLED;
+}
+
+static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
+{
+       struct net_device *netdev = adapter->netdev;
+       u32 mask, i = 0, shared_int = true;
+       u32 irq = adapter->pdev->irq;
+
+       *data = 0;
+
+       /* Hook up test interrupt handler just for this test */
+       if (adapter->msix_entries) {
+               /* NOTE: we don't test MSI-X interrupts here, yet */
+               return 0;
+       } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
+               shared_int = false;
+               if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
+                               netdev)) {
+                       *data = 1;
+                       return -1;
+               }
+       } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
+                               netdev->name, netdev)) {
+               shared_int = false;
+       } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
+                              netdev->name, netdev)) {
+               *data = 1;
+               return -1;
+       }
+       DPRINTK(HW, INFO, "testing %s interrupt\n",
+               (shared_int ? "shared" : "unshared"));
+
+       /* Disable all the interrupts */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       msleep(10);
+
+       /* Test each interrupt */
+       for (; i < 10; i++) {
+               /* Interrupt to test */
+               mask = 1 << i;
+
+               if (!shared_int) {
+                       /*
+                        * Disable the interrupts to be reported in
+                        * the cause register and then force the same
+                        * interrupt and see if one gets posted.  If
+                        * an interrupt was posted to the bus, the
+                        * test failed.
+                        */
+                       adapter->test_icr = 0;
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
+                                       ~mask & 0x00007FFF);
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
+                                       ~mask & 0x00007FFF);
+                       msleep(10);
+
+                       if (adapter->test_icr & mask) {
+                               *data = 3;
+                               break;
+                       }
+               }
+
+               /*
+                * Enable the interrupt to be reported in the cause
+                * register and then force the same interrupt and see
+                * if one gets posted.  If an interrupt was not posted
+                * to the bus, the test failed.
+                */
+               adapter->test_icr = 0;
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
+               msleep(10);
+
+               if (!(adapter->test_icr &mask)) {
+                       *data = 4;
+                       break;
+               }
+
+               if (!shared_int) {
+                       /*
+                        * Disable the other interrupts to be reported in
+                        * the cause register and then force the other
+                        * interrupts and see if any get posted.  If
+                        * an interrupt was posted to the bus, the
+                        * test failed.
+                        */
+                       adapter->test_icr = 0;
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
+                                       ~mask & 0x00007FFF);
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
+                                       ~mask & 0x00007FFF);
+                       msleep(10);
+
+                       if (adapter->test_icr) {
+                               *data = 5;
+                               break;
+                       }
+               }
+       }
+
+       /* Disable all the interrupts */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
+       msleep(10);
+
+       /* Unhook test interrupt handler */
+       free_irq(irq, netdev);
+
+       return *data;
+}
+
+static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
+       struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       int i;
+
+       if (tx_ring->desc && tx_ring->tx_buffer_info) {
+               for (i = 0; i < tx_ring->count; i++) {
+                       struct ixgbe_tx_buffer *buf =
+                                       &(tx_ring->tx_buffer_info[i]);
+                       if (buf->dma)
+                               pci_unmap_single(pdev, buf->dma, buf->length,
+                                                PCI_DMA_TODEVICE);
+                       if (buf->skb)
+                               dev_kfree_skb(buf->skb);
+               }
+       }
+
+       if (rx_ring->desc && rx_ring->rx_buffer_info) {
+               for (i = 0; i < rx_ring->count; i++) {
+                       struct ixgbe_rx_buffer *buf =
+                                       &(rx_ring->rx_buffer_info[i]);
+                       if (buf->dma)
+                               pci_unmap_single(pdev, buf->dma,
+                                                IXGBE_RXBUFFER_2048,
+                                                PCI_DMA_FROMDEVICE);
+                       if (buf->skb)
+                               dev_kfree_skb(buf->skb);
+               }
+       }
+
+       if (tx_ring->desc) {
+               pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
+                                   tx_ring->dma);
+               tx_ring->desc = NULL;
+       }
+       if (rx_ring->desc) {
+               pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
+                                   rx_ring->dma);
+               rx_ring->desc = NULL;
+       }
+
+       kfree(tx_ring->tx_buffer_info);
+       tx_ring->tx_buffer_info = NULL;
+       kfree(rx_ring->rx_buffer_info);
+       rx_ring->rx_buffer_info = NULL;
+
+       return;
+}
+
+static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
+       struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       u32 rctl, reg_data;
+       int i, ret_val;
+
+       /* Setup Tx descriptor ring and Tx buffers */
+
+       if (!tx_ring->count)
+               tx_ring->count = IXGBE_DEFAULT_TXD;
+
+       tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
+                                         sizeof(struct ixgbe_tx_buffer),
+                                         GFP_KERNEL);
+       if (!(tx_ring->tx_buffer_info)) {
+               ret_val = 1;
+               goto err_nomem;
+       }
+
+       tx_ring->size = tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc);
+       tx_ring->size = ALIGN(tx_ring->size, 4096);
+       if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
+                                                  &tx_ring->dma))) {
+               ret_val = 2;
+               goto err_nomem;
+       }
+       tx_ring->next_to_use = tx_ring->next_to_clean = 0;
+
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
+                       ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
+                       ((u64) tx_ring->dma >> 32));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
+                       tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
+       reg_data |= IXGBE_HLREG0_TXPADEN;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
+       reg_data |= IXGBE_TXDCTL_ENABLE;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
+
+       for (i = 0; i < tx_ring->count; i++) {
+               struct ixgbe_legacy_tx_desc *desc = IXGBE_TX_DESC(*tx_ring, i);
+               struct sk_buff *skb;
+               unsigned int size = 1024;
+
+               skb = alloc_skb(size, GFP_KERNEL);
+               if (!skb) {
+                       ret_val = 3;
+                       goto err_nomem;
+               }
+               skb_put(skb, size);
+               tx_ring->tx_buffer_info[i].skb = skb;
+               tx_ring->tx_buffer_info[i].length = skb->len;
+               tx_ring->tx_buffer_info[i].dma =
+                       pci_map_single(pdev, skb->data, skb->len,
+                                       PCI_DMA_TODEVICE);
+               desc->buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
+               desc->lower.data = cpu_to_le32(skb->len);
+               desc->lower.data |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
+                                               IXGBE_TXD_CMD_IFCS |
+                                               IXGBE_TXD_CMD_RS);
+               desc->upper.data = 0;
+       }
+
+       /* Setup Rx Descriptor ring and Rx buffers */
+
+       if (!rx_ring->count)
+               rx_ring->count = IXGBE_DEFAULT_RXD;
+
+       rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
+                                         sizeof(struct ixgbe_rx_buffer),
+                                         GFP_KERNEL);
+       if (!(rx_ring->rx_buffer_info)) {
+               ret_val = 4;
+               goto err_nomem;
+       }
+
+       rx_ring->size = rx_ring->count * sizeof(struct ixgbe_legacy_rx_desc);
+       rx_ring->size = ALIGN(rx_ring->size, 4096);
+       if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
+                                                  &rx_ring->dma))) {
+               ret_val = 5;
+               goto err_nomem;
+       }
+       rx_ring->next_to_use = rx_ring->next_to_clean = 0;
+
+       rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
+                       ((u64)rx_ring->dma & 0xFFFFFFFF));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
+                       ((u64) rx_ring->dma >> 32));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
+       reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
+       reg_data &= ~IXGBE_HLREG0_LPBK;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
+#define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
+                                                  Threshold Size mask */
+       reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
+#define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
+       reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
+       reg_data |= adapter->hw.mac.mc_filter_type;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
+       reg_data |= IXGBE_RXDCTL_ENABLE;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
+
+       rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
+
+       for (i = 0; i < rx_ring->count; i++) {
+               struct ixgbe_legacy_rx_desc *rx_desc =
+                                       IXGBE_RX_DESC(*rx_ring, i);
+               struct sk_buff *skb;
+
+               skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
+               if (!skb) {
+                       ret_val = 6;
+                       goto err_nomem;
+               }
+               skb_reserve(skb, NET_IP_ALIGN);
+               rx_ring->rx_buffer_info[i].skb = skb;
+               rx_ring->rx_buffer_info[i].dma =
+                       pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
+                                      PCI_DMA_FROMDEVICE);
+               rx_desc->buffer_addr =
+                               cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
+               memset(skb->data, 0x00, skb->len);
+       }
+
+       return 0;
+
+err_nomem:
+       ixgbe_free_desc_rings(adapter);
+       return ret_val;
+}
+
+static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 reg_data;
+
+       /* right now we only support MAC loopback in the driver */
+
+       /* Setup MAC loopback */
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
+       reg_data |= IXGBE_HLREG0_LPBK;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
+       reg_data &= ~IXGBE_AUTOC_LMS_MASK;
+       reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
+
+       /* Disable Atlas Tx lanes; re-enabled in reset path */
+       if (hw->mac.type == ixgbe_mac_82598EB) {
+               u8 atlas;
+
+               ixgbe_read_analog_reg8(&adapter->hw,
+                                      IXGBE_ATLAS_PDN_LPBK, &atlas);
+               atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
+               ixgbe_write_analog_reg8(&adapter->hw,
+                                       IXGBE_ATLAS_PDN_LPBK, atlas);
+
+               ixgbe_read_analog_reg8(&adapter->hw,
+                                      IXGBE_ATLAS_PDN_10G, &atlas);
+               atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
+               ixgbe_write_analog_reg8(&adapter->hw,
+                                       IXGBE_ATLAS_PDN_10G, atlas);
+
+               ixgbe_read_analog_reg8(&adapter->hw,
+                                      IXGBE_ATLAS_PDN_1G, &atlas);
+               atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
+               ixgbe_write_analog_reg8(&adapter->hw,
+                                       IXGBE_ATLAS_PDN_1G, atlas);
+
+               ixgbe_read_analog_reg8(&adapter->hw,
+                                      IXGBE_ATLAS_PDN_AN, &atlas);
+               atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
+               ixgbe_write_analog_reg8(&adapter->hw,
+                                       IXGBE_ATLAS_PDN_AN, atlas);
+       }
+
+       return 0;
+}
+
+static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
+{
+       u32 reg_data;
+
+       reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
+       reg_data &= ~IXGBE_HLREG0_LPBK;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
+}
+
+static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
+                                      unsigned int frame_size)
+{
+       memset(skb->data, 0xFF, frame_size);
+       frame_size &= ~1;
+       memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
+       memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
+       memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
+}
+
+static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
+                                    unsigned int frame_size)
+{
+       frame_size &= ~1;
+       if (*(skb->data + 3) == 0xFF) {
+               if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
+                   (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
+                       return 0;
+               }
+       }
+       return 13;
+}
+
+static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
+       struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
+       struct pci_dev *pdev = adapter->pdev;
+       int i, j, k, l, lc, good_cnt, ret_val = 0;
+       unsigned long time;
+
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
+
+       /*
+        * Calculate the loop count based on the largest descriptor ring
+        * The idea is to wrap the largest ring a number of times using 64
+        * send/receive pairs during each loop
+        */
+
+       if (rx_ring->count <= tx_ring->count)
+               lc = ((tx_ring->count / 64) * 2) + 1;
+       else
+               lc = ((rx_ring->count / 64) * 2) + 1;
+
+       k = l = 0;
+       for (j = 0; j <= lc; j++) {
+               for (i = 0; i < 64; i++) {
+                       ixgbe_create_lbtest_frame(
+                                       tx_ring->tx_buffer_info[k].skb,
+                                       1024);
+                       pci_dma_sync_single_for_device(pdev,
+                               tx_ring->tx_buffer_info[k].dma,
+                               tx_ring->tx_buffer_info[k].length,
+                               PCI_DMA_TODEVICE);
+                       if (unlikely(++k == tx_ring->count))
+                               k = 0;
+               }
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
+               msleep(200);
+               /* set the start time for the receive */
+               time = jiffies;
+               good_cnt = 0;
+               do {
+                       /* receive the sent packets */
+                       pci_dma_sync_single_for_cpu(pdev,
+                                       rx_ring->rx_buffer_info[l].dma,
+                                       IXGBE_RXBUFFER_2048,
+                                       PCI_DMA_FROMDEVICE);
+                       ret_val = ixgbe_check_lbtest_frame(
+                                       rx_ring->rx_buffer_info[l].skb, 1024);
+                       if (!ret_val)
+                               good_cnt++;
+                       if (++l == rx_ring->count)
+                               l = 0;
+                       /*
+                        * time + 20 msecs (200 msecs on 2.4) is more than
+                        * enough time to complete the receives, if it's
+                        * exceeded, break and error off
+                        */
+               } while (good_cnt < 64 && jiffies < (time + 20));
+               if (good_cnt != 64) {
+                       /* ret_val is the same as mis-compare */
+                       ret_val = 13;
+                       break;
+               }
+               if (jiffies >= (time + 20)) {
+                       /* Error code for time out error */
+                       ret_val = 14;
+                       break;
+               }
+       }
+
+       return ret_val;
+}
+
+static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
+{
+       *data = ixgbe_setup_desc_rings(adapter);
+       if (*data)
+               goto out;
+       *data = ixgbe_setup_loopback_test(adapter);
+       if (*data)
+               goto err_loopback;
+       *data = ixgbe_run_loopback_test(adapter);
+       ixgbe_loopback_cleanup(adapter);
+
+err_loopback:
+       ixgbe_free_desc_rings(adapter);
+out:
+       return *data;
+}
+
+static int ixgbe_diag_test_count(struct net_device *netdev)
+{
+       return IXGBE_TEST_LEN;
+}
+
+static void ixgbe_diag_test(struct net_device *netdev,
+                            struct ethtool_test *eth_test, u64 *data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       bool if_running = netif_running(netdev);
+
+       set_bit(__IXGBE_TESTING, &adapter->state);
+       if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
+               /* Offline tests */
+
+               DPRINTK(HW, INFO, "offline testing starting\n");
+
+               /* Link test performed before hardware reset so autoneg doesn't
+                * interfere with test result */
+               if (ixgbe_link_test(adapter, &data[4]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               if (if_running)
+                       /* indicate we're in test mode */
+                       dev_close(netdev);
+               else
+                       ixgbe_reset(adapter);
+
+               DPRINTK(HW, INFO, "register testing starting\n");
+               if (ixgbe_reg_test(adapter, &data[0]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               ixgbe_reset(adapter);
+               DPRINTK(HW, INFO, "eeprom testing starting\n");
+               if (ixgbe_eeprom_test(adapter, &data[1]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               ixgbe_reset(adapter);
+               DPRINTK(HW, INFO, "interrupt testing starting\n");
+               if (ixgbe_intr_test(adapter, &data[2]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               ixgbe_reset(adapter);
+               DPRINTK(HW, INFO, "loopback testing starting\n");
+               if (ixgbe_loopback_test(adapter, &data[3]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               ixgbe_reset(adapter);
+
+               clear_bit(__IXGBE_TESTING, &adapter->state);
+               if (if_running)
+                       dev_open(netdev);
+       } else {
+               DPRINTK(HW, INFO, "online testing starting\n");
+               /* Online tests */
+               if (ixgbe_link_test(adapter, &data[4]))
+                       eth_test->flags |= ETH_TEST_FL_FAILED;
+
+               /* Online tests aren't run; pass by default */
+               data[0] = 0;
+               data[1] = 0;
+               data[2] = 0;
+               data[3] = 0;
+
+               clear_bit(__IXGBE_TESTING, &adapter->state);
+       }
+       msleep_interruptible(4 * 1000);
+}
+
+static void ixgbe_get_wol(struct net_device *netdev,
+                          struct ethtool_wolinfo *wol)
+{
+       wol->supported = 0;
+       wol->wolopts = 0;
+
+       return;
+}
+
+static int ixgbe_nway_reset(struct net_device *netdev)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       if (netif_running(netdev))
+               ixgbe_reinit_locked(adapter);
+
+       return 0;
+}
+
+static int ixgbe_phys_id(struct net_device *netdev, u32 data)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       u32 led_reg = IXGBE_READ_REG(&adapter->hw, IXGBE_LEDCTL);
+       u32 i;
+
+       if (!data || data > 300)
+               data = 300;
+
+       for (i = 0; i < (data * 1000); i += 400) {
+               ixgbe_led_on(&adapter->hw, IXGBE_LED_ON);
+               msleep_interruptible(200);
+               ixgbe_led_off(&adapter->hw, IXGBE_LED_ON);
+               msleep_interruptible(200);
+       }
+
+       /* Restore LED settings */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
+
+       return 0;
+}
+
+static int ixgbe_get_coalesce(struct net_device *netdev,
+                              struct ethtool_coalesce *ec)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
+#ifndef CONFIG_IXGBE_NAPI
+       ec->rx_max_coalesced_frames_irq = adapter->rx_ring[0].work_limit;
+#endif
+
+       /* only valid if in constant ITR mode */
+       if (adapter->itr_setting == 0)
+               ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
+
+       return 0;
+}
+
+static int ixgbe_set_coalesce(struct net_device *netdev,
+                              struct ethtool_coalesce *ec)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       if (ec->tx_max_coalesced_frames_irq)
+               adapter->tx_ring[0].work_limit = 
ec->tx_max_coalesced_frames_irq;
+
+#ifndef CONFIG_IXGBE_NAPI
+       if (ec->rx_max_coalesced_frames_irq)
+               adapter->rx_ring[0].work_limit = 
ec->rx_max_coalesced_frames_irq;
+
+#endif
+       if (ec->rx_coalesce_usecs > 3) {
+               struct ixgbe_hw *hw = &adapter->hw;
+               int i;
+               /* store the value in ints/second */
+               adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
+
+               for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++){
+                       struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
+                       if (q_vector->txr_count && !q_vector->rxr_count)
+                               q_vector->eitr = (adapter->eitr_param >> 1);
+                       else
+                               /* rx only */
+                               q_vector->eitr = adapter->eitr_param;
+                       IXGBE_WRITE_REG(hw, IXGBE_EITR(i),
+                                     EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
+               }
+
+               /* static value of interrupt rate */
+               adapter->itr_setting = adapter->eitr_param;
+       } else {
+               /* 1,2,3 means dynamic mode */
+               adapter->itr_setting = ec->rx_coalesce_usecs;
+       }
+
+       if (netif_running(netdev))
+               ixgbe_reinit_locked(adapter);
+
+       return 0;
+}
+
+
+static struct ethtool_ops ixgbe_ethtool_ops = {
+       .get_settings           = ixgbe_get_settings,
+       .set_settings           = ixgbe_set_settings,
+       .get_drvinfo            = ixgbe_get_drvinfo,
+       .get_regs_len           = ixgbe_get_regs_len,
+       .get_regs               = ixgbe_get_regs,
+       .get_wol                = ixgbe_get_wol,
+       .nway_reset             = ixgbe_nway_reset,
+       .get_link               = ethtool_op_get_link,
+       .get_eeprom_len         = ixgbe_get_eeprom_len,
+       .get_eeprom             = ixgbe_get_eeprom,
+       .set_eeprom             = ixgbe_set_eeprom,
+       .get_ringparam          = ixgbe_get_ringparam,
+       .set_ringparam          = ixgbe_set_ringparam,
+       .get_pauseparam         = ixgbe_get_pauseparam,
+       .set_pauseparam         = ixgbe_set_pauseparam,
+       .get_rx_csum            = ixgbe_get_rx_csum,
+       .set_rx_csum            = ixgbe_set_rx_csum,
+       .get_tx_csum            = ixgbe_get_tx_csum,
+       .set_tx_csum            = ixgbe_set_tx_csum,
+       .get_sg                 = ethtool_op_get_sg,
+       .set_sg                 = ethtool_op_set_sg,
+       .get_msglevel           = ixgbe_get_msglevel,
+       .set_msglevel           = ixgbe_set_msglevel,
+#ifdef NETIF_F_TSO
+       .get_tso                = ethtool_op_get_tso,
+       .set_tso                = ixgbe_set_tso,
+#endif
+       .self_test_count        = ixgbe_diag_test_count,
+       .self_test              = ixgbe_diag_test,
+       .get_strings            = ixgbe_get_strings,
+       .phys_id                = ixgbe_phys_id,
+       .get_stats_count        = ixgbe_get_stats_count,
+       .get_ethtool_stats      = ixgbe_get_ethtool_stats,
+#ifdef ETHTOOL_GPERMADDR
+       .get_perm_addr          = ethtool_op_get_perm_addr,
+#endif
+       .get_coalesce           = ixgbe_get_coalesce,
+       .set_coalesce           = ixgbe_set_coalesce,
+#ifndef IXGBE_NO_INET_LRO
+       .get_flags              = ethtool_op_get_flags,
+       .set_flags              = ethtool_op_set_flags,
+#endif
+};
+
+void ixgbe_set_ethtool_ops(struct net_device *netdev)
+{
+       SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
+}
+#endif /* SIOCETHTOOL */
diff -r b790b287bf47 -r 98897f04b338 drivers/net/ixgbe/ixgbe_main.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/ixgbe/ixgbe_main.c    Fri Jan 30 10:52:47 2009 +0000
@@ -0,0 +1,5464 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2008 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@xxxxxxxxxxxxxxxxxxxxx>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+
+/******************************************************************************
+ Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
+******************************************************************************/
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/vmalloc.h>
+#include <linux/string.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/ipv6.h>
+#ifdef NETIF_F_TSO
+#include <net/checksum.h>
+#ifdef NETIF_F_TSO6
+#include <net/ip6_checksum.h>
+#endif
+#endif
+#ifdef SIOCETHTOOL
+#include <linux/ethtool.h>
+#endif
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#endif
+
+#include "ixgbe.h"
+
+char ixgbe_driver_name[] = "ixgbe";
+static const char ixgbe_driver_string[] =
+       "Intel(R) 10 Gigabit PCI Express Network Driver";
+#define DRV_HW_PERF
+
+#ifndef CONFIG_IXGBE_NAPI
+#define DRIVERNAPI
+#else
+#define DRIVERNAPI "-NAPI"
+#endif
+
+#define DRV_VERSION "1.3.56.5" DRIVERNAPI DRV_HW_PERF
+const char ixgbe_driver_version[] = DRV_VERSION;
+static char ixgbe_copyright[] = "Copyright (c) 1999-2008 Intel Corporation.";
+/* ixgbe_pci_tbl - PCI Device ID Table
+ *
+ * Wildcard entries (PCI_ANY_ID) should come last
+ * Last entry must be all 0s
+ *
+ * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
+ *   Class, Class Mask, private data (not used) }
+ */
+static struct pci_device_id ixgbe_pci_tbl[] = {
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AT)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_CX4)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_XF_LR)},
+       {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM)},
+       /* required last entry */
+       {0, }
+};
+MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
+
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
+                            void *p);
+static struct notifier_block dca_notifier = {
+       .notifier_call = ixgbe_notify_dca,
+       .next          = NULL,
+       .priority      = 0
+};
+#endif
+
+MODULE_AUTHOR("Intel Corporation, <linux.nics@xxxxxxxxx>");
+MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+#define DEFAULT_DEBUG_LEVEL_SHIFT 3
+
+static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
+{
+       u32 ctrl_ext;
+
+       /* Let firmware take over control of h/w */
+       ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
+                       ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
+}
+
+static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
+{
+       u32 ctrl_ext;
+
+       /* Let firmware know the driver has taken over */
+       ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
+                       ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
+}
+
+static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
+                           u8 msix_vector)
+{
+       u32 ivar, index;
+
+       msix_vector |= IXGBE_IVAR_ALLOC_VAL;
+       index = (int_alloc_entry >> 2) & 0x1F;
+       ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
+       ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
+       ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
+}
+
+static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
+                                             struct ixgbe_tx_buffer
+                                             *tx_buffer_info)
+{
+       if (tx_buffer_info->dma) {
+               pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
+                              tx_buffer_info->length, PCI_DMA_TODEVICE);
+               tx_buffer_info->dma = 0;
+       }
+       if (tx_buffer_info->skb) {
+               dev_kfree_skb_any(tx_buffer_info->skb);
+               tx_buffer_info->skb = NULL;
+       }
+       /* tx_buffer_info must be completely set up in the transmit path */
+}
+
+static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
+                                       struct ixgbe_ring *tx_ring,
+                                       unsigned int eop)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 head, tail;
+
+       /* Detect a transmit hang in hardware, this serializes the
+        * check with the clearing of time_stamp and movement of eop */
+       head = IXGBE_READ_REG(hw, tx_ring->head);
+       tail = IXGBE_READ_REG(hw, tx_ring->tail);
+       adapter->detect_tx_hung = false;
+       if ((head != tail) &&
+           tx_ring->tx_buffer_info[eop].time_stamp &&
+           time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
+           !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
+               /* detected Tx unit hang */
+               union ixgbe_adv_tx_desc *tx_desc;
+               tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
+               DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
+                       "  Tx Queue             <%d>\n"
+                       "  TDH, TDT             <%x>, <%x>\n"
+                       "  next_to_use          <%x>\n"
+                       "  next_to_clean        <%x>\n"
+                       "tx_buffer_info[next_to_clean]\n"
+                       "  time_stamp           <%lx>\n"
+                       "  jiffies              <%lx>\n",
+                       tx_ring->queue_index,
+                       head, tail,
+                       tx_ring->next_to_use, eop,
+                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
+               return true;
+       }
+
+       return false;
+}
+
+#define IXGBE_MAX_TXD_PWR      14
+#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
+
+/* Tx Descriptors needed, worst case */
+#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
+                        (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
+#ifdef MAX_SKB_FRAGS
+#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
+       MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1)      /* for context */
+#else
+#define DESC_NEEDED TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD)
+#endif
+
+#define GET_TX_HEAD_FROM_RING(ring) (\
+       *(volatile u32 *) \
+       ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
+static void ixgbe_tx_timeout(struct net_device *netdev);
+
+/**
+ * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
+ * @adapter: board private structure
+ * @tx_ring: tx ring to clean
+ **/
+static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
+                               struct ixgbe_ring *tx_ring)
+{
+       union ixgbe_adv_tx_desc *tx_desc;
+       struct ixgbe_tx_buffer *tx_buffer_info;
+       struct net_device *netdev = adapter->netdev;
+       struct sk_buff *skb;
+       unsigned int i;
+       u32 head, oldhead;
+       unsigned int count = 0;
+       unsigned int total_bytes = 0, total_packets = 0;
+
+       rmb();
+       head = GET_TX_HEAD_FROM_RING(tx_ring);
+       head = le32_to_cpu(head);
+       i = tx_ring->next_to_clean;
+       while (1) {
+               while (i != head) {
+                       tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
+                       tx_buffer_info = &tx_ring->tx_buffer_info[i];
+                       skb = tx_buffer_info->skb;
+
+                       if (skb) {
+#ifdef NETIF_F_TSO
+                               unsigned int segs, bytecount;
+
+                               /* gso_segs is currently only valid for tcp */
+                               segs = skb_shinfo(skb)->gso_segs ?: 1;
+                               /* multiply data chunks by size of headers */
+                               bytecount = ((segs - 1) * skb_headlen(skb)) +
+                                           skb->len;
+                               total_packets += segs;
+                               total_bytes += bytecount;
+#else
+                               total_packets++;
+                               total_bytes += skb->len;
+#endif
+                       }
+
+                       ixgbe_unmap_and_free_tx_resource(adapter,
+                                                        tx_buffer_info);
+
+                       i++;
+                       if (i == tx_ring->count)
+                               i = 0;
+
+                       count++;
+                       if (count == tx_ring->count)
+                               goto done_cleaning;
+               }
+               oldhead = head;
+               rmb();
+               head = GET_TX_HEAD_FROM_RING(tx_ring);
+               head = le32_to_cpu(head);
+               if (head == oldhead)
+                       goto done_cleaning;
+       } /* while (1) */
+
+done_cleaning:
+       tx_ring->next_to_clean = i;
+
+#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
+       if (unlikely(count && netif_carrier_ok(netdev) &&
+                    (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
+               /* Make sure that anybody stopping the queue after this
+                * sees the new next_to_clean.
+                */
+               smp_mb();
+#ifdef HAVE_TX_MQ
+               if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
+                   !test_bit(__IXGBE_DOWN, &adapter->state)) {
+                       netif_wake_subqueue(netdev, tx_ring->queue_index);
+                       ++adapter->restart_queue;
+               }
+#else
+               if (netif_queue_stopped(netdev) &&
+                   !test_bit(__IXGBE_DOWN, &adapter->state)) {
+                       netif_wake_queue(netdev);
+                       ++adapter->restart_queue;
+               }
+#endif
+       }
+
+       if (adapter->detect_tx_hung) {
+               if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
+                       /* schedule immediate reset if we believe we hung */
+                       DPRINTK(PROBE, INFO,
+                               "tx hang %d detected, resetting adapter\n",
+                               adapter->tx_timeout_count + 1);
+                       ixgbe_tx_timeout(adapter->netdev);
+               }
+       }
+
+       /* re-arm the interrupt */
+       if ((total_packets >= tx_ring->work_limit) ||
+           (count == tx_ring->count))
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
+
+       tx_ring->total_bytes += total_bytes;
+       tx_ring->total_packets += total_packets;
+       tx_ring->stats.packets += total_packets;
+       tx_ring->stats.bytes += total_bytes;
+       adapter->net_stats.tx_bytes += total_bytes;
+       adapter->net_stats.tx_packets += total_packets;
+       return (total_packets ? true : false);
+}
+
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
+                                struct ixgbe_ring *rx_ring)
+{
+       u32 rxctrl;
+       int cpu = get_cpu();
+       int q = rx_ring - adapter->rx_ring;
+
+       if (rx_ring->cpu != cpu) {
+               rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
+               rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
+               rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
+               rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
+               rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
+               rx_ring->cpu = cpu;
+       }
+       put_cpu();
+}
+
+static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
+                                struct ixgbe_ring *tx_ring)
+{
+       u32 txctrl;
+       int cpu = get_cpu();
+       int q = tx_ring - adapter->tx_ring;
+
+       if (tx_ring->cpu != cpu) {
+               txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
+               txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
+               txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
+               txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
+               tx_ring->cpu = cpu;
+       }
+       put_cpu();
+}
+
+static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
+{
+       int i;
+
+       if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
+               return;
+
+       for (i = 0; i < adapter->num_tx_queues; i++) {
+               adapter->tx_ring[i].cpu = -1;
+               ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
+       }
+       for (i = 0; i < adapter->num_rx_queues; i++) {
+               adapter->rx_ring[i].cpu = -1;
+               ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
+       }
+}
+
+static int __ixgbe_notify_dca(struct device *dev, void *data)
+{
+       struct net_device *netdev = dev_get_drvdata(dev);
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       unsigned long event = *(unsigned long *)data;
+
+       switch (event) {
+       case DCA_PROVIDER_ADD:
+               /* if we're already enabled, don't do it again */
+               if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                       break;
+               /* Always use CB2 mode, difference is masked
+                * in the CB driver. */
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
+               if (dca_add_requester(dev) == 0) {
+                       adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
+                       ixgbe_setup_dca(adapter);
+                       break;
+               }
+               /* Fall Through since DCA is disabled. */
+       case DCA_PROVIDER_REMOVE:
+               if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
+                       dca_remove_requester(dev);
+                       adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
+               }
+               break;
+       }
+
+       return 0;
+}
+
+#endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
+/**
+ * ixgbe_receive_skb - Send a completed packet up the stack
+ * @adapter: board private structure
+ * @skb: packet to send up
+ * @status: hardware indication of status of receive
+ * @rx_ring: rx descriptor ring (for a specific queue) to setup
+ * @rx_desc: rx descriptor
+ **/
+static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
+                              struct sk_buff *skb, u8 status,
+                              struct ixgbe_ring *ring,
+                              union ixgbe_adv_rx_desc *rx_desc)
+{
+       int ret;
+       bool is_vlan = (status & IXGBE_RXD_STAT_VP);
+       u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
+
+#ifndef IXGBE_NO_INET_LRO
+       if (adapter->netdev->features & NETIF_F_LRO &&
+           skb->ip_summed == CHECKSUM_UNNECESSARY) {
+#ifdef NETIF_F_HW_VLAN_TX
+               if (adapter->vlgrp && is_vlan && (tag != 0))
+                       lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
+                                                    adapter->vlgrp, tag,
+                                                    rx_desc);
+               else
+#endif
+                       lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
+               ring->lro_used = true;
+       } else {
+#endif /* IXGBE_NO_INET_LRO */
+#ifdef CONFIG_IXGBE_NAPI
+               if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
+#ifdef NETIF_F_HW_VLAN_TX
+                       if (adapter->vlgrp && is_vlan && (tag != 0))
+                               vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 
tag);
+                       else
+                               netif_receive_skb(skb);
+#else
+                       netif_receive_skb(skb);
+#endif
+               } else {
+#endif /* CONFIG_IXGBE_NAPI */
+
+#ifdef NETIF_F_HW_VLAN_TX
+                       if (adapter->vlgrp && is_vlan && (tag != 0))
+                               ret = vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
+                       else
+                               ret = netif_rx(skb);
+#else
+                       ret = netif_rx(skb);
+#endif
+#ifndef CONFIG_IXGBE_NAPI
+                       if (ret == NET_RX_DROP)
+                               adapter->rx_dropped_backlog++;
+#endif
+#ifdef CONFIG_IXGBE_NAPI
+               }
+#endif /* CONFIG_IXGBE_NAPI */
+#ifndef IXGBE_NO_INET_LRO
+       }
+#endif
+}
+
+/**
+ * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
+ * @adapter: address of board private structure
+ * @status_err: hardware indication of status of receive
+ * @skb: skb currently being received and modified
+ **/
+static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
+                                     u32 status_err, struct sk_buff *skb)
+{
+       skb->ip_summed = CHECKSUM_NONE;
+
+       /* Rx csum disabled */
+       if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
+               return;
+
+       /* if IP and error */
+       if ((status_err & IXGBE_RXD_STAT_IPCS) &&
+           (status_err & IXGBE_RXDADV_ERR_IPE)) {
+               adapter->hw_csum_rx_error++;
+               return;
+       }
+
+       if (!(status_err & IXGBE_RXD_STAT_L4CS))
+               return;
+
+       if (status_err & IXGBE_RXDADV_ERR_TCPE) {
+               adapter->hw_csum_rx_error++;
+               return;
+       }
+
+       /* It must be a TCP or UDP packet with a valid checksum */
+       skb->ip_summed = CHECKSUM_UNNECESSARY;
+       adapter->hw_csum_rx_good++;
+}
+
+/**
+ * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
+ * @adapter: address of board private structure
+ **/
+static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
+                                   struct ixgbe_ring *rx_ring,
+                                   int cleaned_count)
+{
+       struct pci_dev *pdev = adapter->pdev;
+       union ixgbe_adv_rx_desc *rx_desc;
+       struct ixgbe_rx_buffer *bi;
+       unsigned int i;
+       unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
+
+       i = rx_ring->next_to_use;
+       bi = &rx_ring->rx_buffer_info[i];
+
+       while (cleaned_count--) {
+               rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
+
+               if (!bi->page_dma &&
+                   (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
+                       if (!bi->page) {
+                               bi->page = alloc_page(GFP_ATOMIC);
+                               if (!bi->page) {
+                                       adapter->alloc_rx_page_failed++;
+                                       goto no_buffers;
+                               }
+                               bi->page_offset = 0;
+                       } else {
+                               /* use a half page if we're re-using */
+                               bi->page_offset ^= (PAGE_SIZE / 2);
+                       }
+
+                       bi->page_dma = pci_map_page(pdev, bi->page,
+                                                   bi->page_offset,
+                                                   (PAGE_SIZE / 2),
+                                                   PCI_DMA_FROMDEVICE);
+               }
+
+               if (!bi->skb) {
+                       struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
+                                                              bufsz);
+
+                       if (!skb) {
+                               adapter->alloc_rx_buff_failed++;
+                               goto no_buffers;
+                       }
+
+                       /*
+                        * Make buffer alignment 2 beyond a 16 byte boundary
+                        * this will result in a 16 byte aligned IP header after
+                        * the 14 byte MAC header is removed
+                        */
+                       skb_reserve(skb, NET_IP_ALIGN);
+
+                       bi->skb = skb;
+                       bi->dma = pci_map_single(pdev, skb->data, bufsz,
+                                                PCI_DMA_FROMDEVICE);
+               }
+               /* Refresh the desc even if buffer_addrs didn't change because
+                * each write-back erases this info. */
+               if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
+                       rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
+                       rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
+               } else {
+                       rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
+               }
+
+               i++;
+               if (i == rx_ring->count)
+                       i = 0;
+               bi = &rx_ring->rx_buffer_info[i];
+       }
+
+no_buffers:
+       if (rx_ring->next_to_use != i) {
+               rx_ring->next_to_use = i;
+               if (i-- == 0)
+                       i = (rx_ring->count - 1);
+
+               /*
+                * Force memory writes to complete before letting h/w
+                * know there are new descriptors to fetch.  (Only
+                * applicable for weak-ordered memory model archs,
+                * such as IA-64).
+                */
+               wmb();
+               writel(i, adapter->hw.hw_addr + rx_ring->tail);
+       }
+}
+
+static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
+{
+       return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
+}
+
+static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
+{
+       return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
+}
+
+#ifndef IXGBE_NO_LRO
+static int lromax = 44;
+
+/**
+ * ixgbe_lro_ring_flush - Indicate packets to upper layer.
+ *
+ * Update IP and TCP header part of head skb if more than one
+ * skb's chained and indicate packets to upper layer.
+ **/
+static void ixgbe_lro_ring_flush(struct ixgbe_lro_list *lrolist,
+                                 struct ixgbe_adapter *adapter,
+                                 struct ixgbe_lro_desc *lrod, u8 status,
+                                 struct ixgbe_ring *rx_ring,
+                                 union ixgbe_adv_rx_desc *rx_desc)
+{
+       struct iphdr *iph;
+       struct tcphdr *th;
+       struct sk_buff *skb;
+       u32 *ts_ptr;
+       struct ixgbe_lro_info *lro_data = &adapter->lro_data;
+       struct net_device *netdev = adapter->netdev;
+
+       hlist_del(&lrod->lro_node);
+       lrolist->active_cnt--;
+
+       skb = lrod->skb;
+
+       if (lrod->append_cnt) {
+               /* incorporate ip header and re-calculate checksum */
+               iph = (struct iphdr *)skb->data;
+               iph->tot_len = ntohs(skb->len);
+               iph->check = 0;
+               iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
+
+               /* incorporate the latest ack into the tcp header */
+               th = (struct tcphdr *) ((char *)skb->data + sizeof(*iph));
+               th->ack_seq = lrod->ack_seq;
+               th->window = lrod->window;
+
+               /* incorporate latest timestamp into the tcp header */
+               if (lrod->timestamp) {
+                       ts_ptr = (u32 *)(th + 1);
+                       ts_ptr[1] = htonl(lrod->tsval);
+                       ts_ptr[2] = lrod->tsecr;
+               }
+       }
+
+#ifdef NETIF_F_TSO
+       skb_shinfo(skb)->gso_size = lrod->mss;
+#endif
+       ixgbe_receive_skb(adapter, skb, status, rx_ring, rx_desc);
+
+       netdev->last_rx = jiffies;
+       lro_data->stats.coal += lrod->append_cnt + 1;
+       lro_data->stats.flushed++;
+
+       lrod->skb = NULL;
+       lrod->last_skb = NULL;
+       lrod->timestamp = 0;
+       lrod->append_cnt = 0;
+       lrod->data_size = 0;
+       hlist_add_head(&lrod->lro_node, &lrolist->free);
+}
+
+static void ixgbe_lro_ring_flush_all(struct ixgbe_lro_list *lrolist,
+                                     struct ixgbe_adapter *adapter, u8 status,
+                                     struct ixgbe_ring *rx_ring,
+                                     union ixgbe_adv_rx_desc *rx_desc)
+{
+       struct ixgbe_lro_desc *lrod;
+       struct hlist_node *node, *node2;
+
+       hlist_for_each_entry_safe(lrod, node, node2, &lrolist->active, lro_node)
+               ixgbe_lro_ring_flush(lrolist, adapter, lrod, status, rx_ring,
+                                    rx_desc);
+}
+
+/*
+ * ixgbe_lro_header_ok - Main LRO function.
+ **/
+static int ixgbe_lro_header_ok(struct ixgbe_lro_info *lro_data,
+                               struct sk_buff *new_skb, struct iphdr *iph,
+                               struct tcphdr *th)
+{
+       int opt_bytes, tcp_data_len;
+       u32 *ts_ptr = NULL;
+
+       /* If we see CE codepoint in IP header, packet is not mergeable */
+       if (INET_ECN_is_ce(ipv4_get_dsfield(iph)))
+               return -1;
+
+       /* ensure there are no options */
+       if ((iph->ihl << 2) != sizeof(*iph))
+               return -1;
+
+       /* .. and the packet is not fragmented */
+       if (iph->frag_off & htons(IP_MF|IP_OFFSET))
+               return -1;
+
+       /* ensure no bits set besides ack or psh */
+       if (th->fin || th->syn || th->rst ||
+           th->urg || th->ece || th->cwr || !th->ack)
+               return -1;
+
+       /* ensure that the checksum is valid */
+       if (new_skb->ip_summed != CHECKSUM_UNNECESSARY)
+               return -1;
+
+       /*
+        * check for timestamps. Since the only option we handle are timestamps,
+        * we only have to handle the simple case of aligned timestamps
+        */
+
+       opt_bytes = (th->doff << 2) - sizeof(*th);
+       if (opt_bytes != 0) {
+               ts_ptr = (u32 *)(th + 1);
+               if ((opt_bytes != TCPOLEN_TSTAMP_ALIGNED) ||
+                       (*ts_ptr != ntohl((TCPOPT_NOP << 24) |
+                       (TCPOPT_NOP << 16) | (TCPOPT_TIMESTAMP << 8) |
+                       TCPOLEN_TIMESTAMP))) {
+                       return -1;
+               }
+       }
+
+       tcp_data_len = ntohs(iph->tot_len) - (th->doff << 2) - sizeof(*iph);
+
+       if (tcp_data_len == 0)
+               return -1;
+
+       return tcp_data_len;
+}
+
+/**
+ * ixgbe_lro_ring_queue - if able, queue skb into lro chain
+ * @lrolist: pointer to structure for lro entries
+ * @adapter: address of board private structure
+ * @new_skb: pointer to current skb being checked
+ * @status: hardware indication of status of receive
+ * @rx_ring: rx descriptor ring (for a specific queue) to setup
+ * @rx_desc: rx descriptor
+ *
+ * Checks whether the skb given is eligible for LRO and if that's
+ * fine chains it to the existing lro_skb based on flowid. If an LRO for
+ * the flow doesn't exist create one.
+ **/
+static int ixgbe_lro_ring_queue(struct ixgbe_lro_list *lrolist,
+                                struct ixgbe_adapter *adapter,
+                                struct sk_buff *new_skb, u8 status,
+                                struct ixgbe_ring *rx_ring,
+                                union ixgbe_adv_rx_desc *rx_desc)
+{
+       struct ethhdr *eh;
+       struct iphdr *iph;
+       struct tcphdr *th, *header_th;
+       int  opt_bytes, header_ok = 1;
+       u32 *ts_ptr = NULL;
+       struct sk_buff *lro_skb;
+       struct ixgbe_lro_desc *lrod;
+       struct hlist_node *node;
+       u32 seq;
+       struct ixgbe_lro_info *lro_data = &adapter->lro_data;
+       int tcp_data_len;
+       u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
+
+       /* Disable LRO when in promiscuous mode, useful for debugging LRO */
+       if (adapter->netdev->flags & IFF_PROMISC)
+               return -1;
+
+       eh = (struct ethhdr *)skb_mac_header(new_skb);
+       iph = (struct iphdr *)(eh + 1);
+
+       /* check to see if it is IPv4/TCP */
+       if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
+            (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
+               return -1;
+
+       /* find the TCP header */
+       th = (struct tcphdr *) (iph + 1);
+
+       tcp_data_len = ixgbe_lro_header_ok(lro_data, new_skb, iph, th);
+       if (tcp_data_len == -1)
+               header_ok = 0;
+
+       /* make sure any packet we are about to chain doesn't include any pad */
+       skb_trim(new_skb, ntohs(iph->tot_len));
+
+       opt_bytes = (th->doff << 2) - sizeof(*th);
+       if (opt_bytes != 0)
+               ts_ptr = (u32 *)(th + 1);
+
+       seq = ntohl(th->seq);
+       /*
+        * we have a packet that might be eligible for LRO,
+        * so see if it matches anything we might expect
+        */
+       hlist_for_each_entry(lrod, node, &lrolist->active, lro_node) {
+               if (lrod->source_port == th->source &&
+                       lrod->dest_port == th->dest &&
+                       lrod->source_ip == iph->saddr &&
+                       lrod->dest_ip == iph->daddr &&
+                       lrod->vlan_tag == tag) {
+
+                       if (!header_ok) {
+                               ixgbe_lro_ring_flush(lrolist, adapter, lrod,
+                                                    status, rx_ring, rx_desc);
+                               return -1;
+                       }
+
+                       if (seq != lrod->next_seq) {
+                               /* out of order packet */
+                               ixgbe_lro_ring_flush(lrolist, adapter, lrod,
+                                                    status, rx_ring, rx_desc);
+                               return -1;
+                       }
+
+                       if (lrod->timestamp) {
+                               u32 tsval = ntohl(*(ts_ptr + 1));
+                               /* make sure timestamp values are increasing */
+                               if (lrod->tsval > tsval || *(ts_ptr + 2) == 0) {
+                                       ixgbe_lro_ring_flush(lrolist, adapter,
+                                                            lrod, status,
+                                                            rx_ring, rx_desc);
+                                       return -1;
+                               }
+                               lrod->tsval = tsval;
+                               lrod->tsecr = *(ts_ptr + 2);
+                       }
+
+                       lro_skb = lrod->skb;
+
+                       lro_skb->len += tcp_data_len;
+                       lro_skb->data_len += tcp_data_len;
+                       lro_skb->truesize += tcp_data_len;
+
+                       lrod->next_seq += tcp_data_len;
+                       lrod->ack_seq = th->ack_seq;
+                       lrod->window = th->window;
+                       lrod->data_size += tcp_data_len;
+                       if (tcp_data_len > lrod->mss)
+                               lrod->mss = tcp_data_len;
+
+                       /* Remove IP and TCP header*/
+                       skb_pull(new_skb, ntohs(iph->tot_len) - tcp_data_len);
+
+                       /* Chain this new skb in frag_list */
+                       if (skb_shinfo(lro_skb)->frag_list != NULL )
+                               lrod->last_skb->next = new_skb;
+                       else
+                               skb_shinfo(lro_skb)->frag_list = new_skb;
+
+                       lrod->last_skb = new_skb ;
+
+                       lrod->append_cnt++;
+
+                       /* New packet with push flag, flush the whole packet. */
+                       if (th->psh) {
+                               header_th =
+                               (struct tcphdr *)(lro_skb->data + sizeof(*iph));
+                               header_th->psh |= th->psh;
+                               ixgbe_lro_ring_flush(lrolist, adapter, lrod,
+                                                    status, rx_ring, rx_desc);
+                               return 0;
+                       }
+
+                       if (lrod->append_cnt >= lro_data->max)
+                               ixgbe_lro_ring_flush(lrolist, adapter, lrod,
+                                                    status, rx_ring, rx_desc);
+
+                       return 0;
+               } /*End of if*/
+       }
+
+       /* start a new packet */
+       if (header_ok && !hlist_empty(&lrolist->free)) {
+               lrod = hlist_entry(lrolist->free.first, struct ixgbe_lro_desc,
+                                  lro_node);
+
+               lrod->skb = new_skb;
+               lrod->source_ip = iph->saddr;
+               lrod->dest_ip = iph->daddr;
+               lrod->source_port = th->source;
+               lrod->dest_port = th->dest;
+               lrod->next_seq = seq + tcp_data_len;
+               lrod->mss = tcp_data_len;
+               lrod->ack_seq = th->ack_seq;
+               lrod->window = th->window;
+               lrod->data_size = tcp_data_len;
+               lrod->vlan_tag = tag;
+
+               /* record timestamp if it is present */
+               if (opt_bytes) {
+                       lrod->timestamp = 1;
+                       lrod->tsval = ntohl(*(ts_ptr + 1));
+                       lrod->tsecr = *(ts_ptr + 2);
+               }
+               /* remove first packet from freelist.. */
+               hlist_del(&lrod->lro_node);
+               /* .. and insert at the front of the active list */
+               hlist_add_head(&lrod->lro_node, &lrolist->active);
+               lrolist->active_cnt++;
+
+               return 0;
+       }
+
+       return -1;
+}
+
+static void ixgbe_lro_ring_exit(struct ixgbe_lro_list *lrolist)
+{
+       struct hlist_node *node, *node2;
+       struct ixgbe_lro_desc *lrod;
+
+       hlist_for_each_entry_safe(lrod, node, node2, &lrolist->active,
+                                 lro_node) {
+               hlist_del(&lrod->lro_node);
+               kfree(lrod);
+       }
+
+       hlist_for_each_entry_safe(lrod, node, node2, &lrolist->free,
+                                 lro_node) {
+               hlist_del(&lrod->lro_node);
+               kfree(lrod);
+       }
+}
+
+static void ixgbe_lro_ring_init(struct ixgbe_lro_list *lrolist,
+                                struct ixgbe_adapter *adapter)
+{
+       int j, bytes;
+       struct ixgbe_lro_desc *lrod;
+
+       bytes = sizeof(struct ixgbe_lro_desc);
+
+       INIT_HLIST_HEAD(&lrolist->free);
+       INIT_HLIST_HEAD(&lrolist->active);
+
+       for (j = 0; j < IXGBE_LRO_MAX; j++) {
+               lrod = kzalloc(bytes, GFP_KERNEL);
+               if (lrod != NULL) {
+                       INIT_HLIST_NODE(&lrod->lro_node);
+                       hlist_add_head(&lrod->lro_node, &lrolist->free);
+               } else {
+                       DPRINTK(PROBE, ERR,
+                               "Allocation for LRO descriptor %u failed\n", j);
+               }
+       }
+}
+
+#endif /* IXGBE_NO_LRO */
+#ifdef CONFIG_IXGBE_NAPI
+static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
+                               struct ixgbe_ring *rx_ring,
+                               int *work_done, int work_to_do)
+#else
+static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
+                               struct ixgbe_ring *rx_ring)
+#endif
+{
+       struct pci_dev *pdev = adapter->pdev;
+       union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
+       struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
+       struct sk_buff *skb;
+       unsigned int i;
+       u32 len, staterr;
+       u16 hdr_info;
+       bool cleaned = false;
+       int cleaned_count = 0;
+#ifndef CONFIG_IXGBE_NAPI
+       int work_to_do = rx_ring->work_limit, local_work_done = 0;
+       int *work_done = &local_work_done;
+#endif
+       unsigned int total_rx_bytes = 0, total_rx_packets = 0;
+
+       i = rx_ring->next_to_clean;
+       rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
+       staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
+       rx_buffer_info = &rx_ring->rx_buffer_info[i];
+
+       while (staterr & IXGBE_RXD_STAT_DD) {
+               u32 upper_len = 0;
+               if (*work_done >= work_to_do)
+                       break;
+               (*work_done)++;
+
+               if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
+                       hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
+                       len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
+                              IXGBE_RXDADV_HDRBUFLEN_SHIFT;
+                       if (hdr_info & IXGBE_RXDADV_SPH)
+                               adapter->rx_hdr_split++;
+                       if (len > IXGBE_RX_HDR_SIZE)
+                               len = IXGBE_RX_HDR_SIZE;
+                       upper_len = le16_to_cpu(rx_desc->wb.upper.length);
+               } else {
+                       len = le16_to_cpu(rx_desc->wb.upper.length);
+               }
+
+#ifndef IXGBE_NO_LLI
+               if (staterr & IXGBE_RXD_STAT_DYNINT)
+                       adapter->lli_int++;
+#endif
+
+               cleaned = true;
+               skb = rx_buffer_info->skb;
+               prefetch(skb->data - NET_IP_ALIGN);
+               rx_buffer_info->skb = NULL;
+
+               if (len && !skb_shinfo(skb)->nr_frags) {
+                       pci_unmap_single(pdev, rx_buffer_info->dma,
+                                        rx_ring->rx_buf_len + NET_IP_ALIGN,
+                                        PCI_DMA_FROMDEVICE);
+                       skb_put(skb, len);
+               }
+
+               if (upper_len) {
+                       pci_unmap_page(pdev, rx_buffer_info->page_dma,
+                                      PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
+                       rx_buffer_info->page_dma = 0;
+                       skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
+                                          rx_buffer_info->page,
+                                          rx_buffer_info->page_offset,
+                                          upper_len);
+
+                       if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
+                           (page_count(rx_buffer_info->page) != 1))
+                               rx_buffer_info->page = NULL;
+                       else
+                               get_page(rx_buffer_info->page);
+
+                       skb->len += upper_len;
+                       skb->data_len += upper_len;
+                       skb->truesize += upper_len;
+               }
+
+               i++;
+               if (i == rx_ring->count)
+                       i = 0;
+               next_buffer = &rx_ring->rx_buffer_info[i];
+
+               next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
+               prefetch(next_rxd);
+
+               cleaned_count++;
+               if (staterr & IXGBE_RXD_STAT_EOP) {
+                       rx_ring->stats.packets++;
+                       rx_ring->stats.bytes += skb->len;
+               } else {
+                       rx_buffer_info->skb = next_buffer->skb;
+                       rx_buffer_info->dma = next_buffer->dma;
+                       next_buffer->skb = skb;
+                       next_buffer->dma = 0;
+                       adapter->non_eop_descs++;
+                       goto next_desc;
+               }
+
+               /* ERR_MASK will only have valid bits if EOP set */
+               if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
+                       dev_kfree_skb_irq(skb);
+                       goto next_desc;
+               }
+
+               ixgbe_rx_checksum(adapter, staterr, skb);
+
+               /* probably a little skewed due to removing CRC */
+               total_rx_bytes += skb->len;
+               total_rx_packets++;
+
+               skb->protocol = eth_type_trans(skb, adapter->netdev);
+#ifndef IXGBE_NO_LRO
+               if (ixgbe_lro_ring_queue(rx_ring->lrolist,
+                               adapter, skb, staterr, rx_ring, rx_desc) == 0) {
+                       adapter->netdev->last_rx = jiffies;
+                       rx_ring->stats.packets++;
+                       if (upper_len)
+                               rx_ring->stats.bytes += upper_len;
+                       else
+                               rx_ring->stats.bytes += skb->len;
+                       goto next_desc;
+               }
+#endif
+               ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
+               adapter->netdev->last_rx = jiffies;
+
+next_desc:
+               rx_desc->wb.upper.status_error = 0;
+
+               /* return some buffers to hardware, one at a time is too slow */
+               if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
+                       ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
+                       cleaned_count = 0;
+               }
+
+               /* use prefetched values */
+               rx_desc = next_rxd;
+               rx_buffer_info = next_buffer;
+
+               staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
+       }
+
+       rx_ring->next_to_clean = i;
+#ifndef IXGBE_NO_LRO
+       ixgbe_lro_ring_flush_all(rx_ring->lrolist, adapter,
+                            staterr, rx_ring, rx_desc);
+#endif /* IXGBE_NO_LRO */
+       cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
+#ifndef IXGBE_NO_INET_LRO
+       if (rx_ring->lro_used) {
+               lro_flush_all(&rx_ring->lro_mgr);
+               rx_ring->lro_used = false;
+       }
+#endif
+
+       if (cleaned_count)
+               ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
+
+       rx_ring->total_packets += total_rx_packets;
+       rx_ring->total_bytes += total_rx_bytes;
+       adapter->net_stats.rx_bytes += total_rx_bytes;
+       adapter->net_stats.rx_packets += total_rx_packets;
+
+#ifndef CONFIG_IXGBE_NAPI
+       /* re-arm the interrupt if we had to bail early and have more work */
+       if (*work_done >= work_to_do)
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, rx_ring->v_idx);
+#endif
+       return cleaned;
+}
+
+#ifdef CONFIG_IXGBE_NAPI
+static int ixgbe_clean_rxonly(struct napi_struct *, int);
+#endif
+/**
+ * ixgbe_configure_msix - Configure MSI-X hardware
+ * @adapter: board private structure
+ *
+ * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
+ * interrupts.
+ **/
+static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_q_vector *q_vector;
+       int i, j, q_vectors, v_idx, r_idx;
+       u32 mask;
+
+       q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
+
+       /* Populate the IVAR table and set the ITR values to the
+        * corresponding register.
+        */
+       for (v_idx = 0; v_idx < q_vectors; v_idx++) {
+               q_vector = &adapter->q_vector[v_idx];
+               /* XXX for_each_bit(...) */
+               r_idx = find_first_bit(q_vector->rxr_idx,
+                                      adapter->num_rx_queues);
+
+               for (i = 0; i < q_vector->rxr_count; i++) {
+                       j = adapter->rx_ring[r_idx].reg_idx;
+                       ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
+                       r_idx = find_next_bit(q_vector->rxr_idx,
+                                             adapter->num_rx_queues,
+                                             r_idx + 1);
+               }
+               r_idx = find_first_bit(q_vector->txr_idx,
+                                      adapter->num_tx_queues);
+
+               for (i = 0; i < q_vector->txr_count; i++) {
+                       j = adapter->tx_ring[r_idx].reg_idx;
+                       ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
+                       r_idx = find_next_bit(q_vector->txr_idx,
+                                             adapter->num_tx_queues,
+                                             r_idx + 1);
+               }
+
+               /* if this is a tx only vector halve the interrupt rate */
+               if (q_vector->txr_count && !q_vector->rxr_count)
+                       q_vector->eitr = (adapter->eitr_param >> 1);
+               else
+                       /* rx only */
+                       q_vector->eitr = adapter->eitr_param;
+
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
+                               EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
+       }
+
+       ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
+#ifdef IXGBE_TCP_TIMER
+       ixgbe_set_ivar(adapter, IXGBE_IVAR_TCP_TIMER_INDEX, ++v_idx);
+#endif
+
+       /* set up to autoclear timer, and the vectors */
+       mask = IXGBE_EIMS_ENABLE_MASK;
+       mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
+}
+
+enum latency_range {
+       lowest_latency = 0,
+       low_latency = 1,
+       bulk_latency = 2,
+       latency_invalid = 255
+};
+
+/**
+ * ixgbe_update_itr - update the dynamic ITR value based on statistics
+ * @adapter: pointer to adapter
+ * @eitr: eitr setting (ints per sec) to give last timeslice
+ * @itr_setting: current throttle rate in ints/second
+ * @packets: the number of packets during this measurement interval
+ * @bytes: the number of bytes during this measurement interval
+ *
+ *      Stores a new ITR value based on packets and byte
+ *      counts during the last interrupt.  The advantage of per interrupt
+ *      computation is faster updates and more accurate ITR for the current
+ *      traffic pattern.  Constants in this function were computed
+ *      based on theoretical maximum wire speed and thresholds were set based
+ *      on testing data as well as attempting to minimize response time
+ *      while increasing bulk throughput.
+ *      this functionality is controlled by the InterruptThrottleRate module
+ *      parameter (see ixgbe_param.c)
+ **/
+static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
+                           u32 eitr, u8 itr_setting,
+                           int packets, int bytes)
+{
+       unsigned int retval = itr_setting;
+       u32 timepassed_us;
+       u64 bytes_perint;
+
+       if (packets == 0)
+               goto update_itr_done;
+
+
+       /* simple throttlerate management
+        *    0-20MB/s lowest (100000 ints/s)
+        *   20-100MB/s low   (20000 ints/s)
+        *  100-1249MB/s bulk (8000 ints/s)
+        */
+       /* what was last interrupt timeslice? */
+       timepassed_us = 1000000/eitr;
+       bytes_perint = bytes / timepassed_us; /* bytes/usec */
+
+       switch (itr_setting) {
+       case lowest_latency:
+               if (bytes_perint > adapter->eitr_low) {
+                       retval = low_latency;
+               }
+               break;
+       case low_latency:
+               if (bytes_perint > adapter->eitr_high) {
+                       retval = bulk_latency;
+               }
+               else if (bytes_perint <= adapter->eitr_low) {
+                       retval = lowest_latency;
+               }
+               break;
+       case bulk_latency:
+               if (bytes_perint <= adapter->eitr_high) {
+                       retval = low_latency;
+               }
+               break;
+       }
+
+update_itr_done:
+       return retval;
+}
+
+static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
+{
+       struct ixgbe_adapter *adapter = q_vector->adapter;
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 new_itr;
+       u8 current_itr, ret_itr;
+       int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
+                             sizeof(struct ixgbe_q_vector);
+       struct ixgbe_ring *rx_ring, *tx_ring;
+
+       r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
+       for (i = 0; i < q_vector->txr_count; i++) {
+               tx_ring = &(adapter->tx_ring[r_idx]);
+               ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
+                                          q_vector->tx_itr,
+                                          tx_ring->total_packets,
+                                          tx_ring->total_bytes);
+               /* if the result for this queue would decrease interrupt
+                * rate for this vector then use that result */
+               q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
+                                   q_vector->tx_itr - 1 : ret_itr);
+               r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
+                                     r_idx + 1);
+       }
+
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       for (i = 0; i < q_vector->rxr_count; i++) {
+               rx_ring = &(adapter->rx_ring[r_idx]);
+               ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
+                                          q_vector->rx_itr,
+                                          rx_ring->total_packets,
+                                          rx_ring->total_bytes);
+               /* if the result for this queue would decrease interrupt
+                * rate for this vector then use that result */
+               q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
+                                   q_vector->rx_itr - 1 : ret_itr);
+               r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
+                                     r_idx + 1);
+       }
+
+       current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
+
+       switch (current_itr) {
+       /* counts and packets in update_itr are dependent on these numbers */
+       case lowest_latency:
+               new_itr = 100000;
+               break;
+       case low_latency:
+               new_itr = 20000; /* aka hwitr = ~200 */
+               break;
+       case bulk_latency:
+       default:
+               new_itr = 8000;
+               break;
+       }
+
+       if (new_itr != q_vector->eitr) {
+               u32 itr_reg;
+               /* do an exponential smoothing */
+               new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
+               q_vector->eitr = new_itr;
+               itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
+               /* must write high and low 16 bits to reset counter */
+               DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, 
itr_reg);
+               IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
+       }
+
+       return;
+}
+
+static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
+           (eicr & IXGBE_EICR_GPI_SDP1)) {
+               DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
+               /* write to clear the interrupt */
+               IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
+       }
+}
+
+static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       adapter->lsc_int++;
+       adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
+       adapter->link_check_timeout = jiffies;
+       if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
+               IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
+               schedule_work(&adapter->watchdog_task);
+       }
+}
+
+static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
+{
+       struct net_device *netdev = data;
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
+
+       if (eicr & IXGBE_EICR_LSC)
+               ixgbe_check_lsc(adapter);
+
+       ixgbe_check_fan_failure(adapter, eicr);
+
+       if (!test_bit(__IXGBE_DOWN, &adapter->state))
+               IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef IXGBE_TCP_TIMER
+static irqreturn_t ixgbe_msix_pba(int irq, void *data)
+{
+       struct net_device *netdev = data;
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       int i;
+
+       u32 pba = readl(adapter->msix_addr + IXGBE_MSIXPBA);
+       for (i = 0; i < MAX_MSIX_COUNT; i++) {
+               if (pba & (1 << i))
+                       adapter->msix_handlers[i](irq, data, regs);
+               else
+                       adapter->pba_zero[i]++;
+       }
+
+       adapter->msix_pba++;
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t ixgbe_msix_tcp_timer(int irq, void *data)
+{
+       struct net_device *netdev = data;
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+
+       adapter->msix_tcp_timer++;
+
+       return IRQ_HANDLED;
+}
+
+#endif /* IXGBE_TCP_TIMER */
+static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
+{
+       struct ixgbe_q_vector *q_vector = data;
+       struct ixgbe_adapter  *adapter = q_vector->adapter;
+       struct ixgbe_ring     *tx_ring;
+       int i, r_idx;
+
+       if (!q_vector->txr_count)
+               return IRQ_HANDLED;
+
+       r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
+       for (i = 0; i < q_vector->txr_count; i++) {
+               tx_ring = &(adapter->tx_ring[r_idx]);
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+               if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                       ixgbe_update_tx_dca(adapter, tx_ring);
+#endif
+               tx_ring->total_bytes = 0;
+               tx_ring->total_packets = 0;
+               ixgbe_clean_tx_irq(adapter, tx_ring);
+               r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
+                                     r_idx + 1);
+       }
+
+       /*
+        * possibly later we can enable tx auto-adjustment if necessary
+        *
+       if (adapter->itr_setting & 3)
+               ixgbe_set_itr_msix(q_vector);
+        */
+
+       return IRQ_HANDLED;
+}
+
+/**
+ * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
+ * @irq: unused
+ * @data: pointer to our q_vector struct for this interrupt vector
+ **/
+static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
+{
+       struct ixgbe_q_vector *q_vector = data;
+       struct ixgbe_adapter  *adapter = q_vector->adapter;
+       struct ixgbe_ring  *rx_ring;
+       int r_idx;
+       int i;
+
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       for (i = 0; i < q_vector->rxr_count; i++) {
+               rx_ring = &(adapter->rx_ring[r_idx]);
+               rx_ring->total_bytes = 0;
+               rx_ring->total_packets = 0;
+#ifndef CONFIG_IXGBE_NAPI
+               ixgbe_clean_rx_irq(adapter, rx_ring);
+
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+               if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                       ixgbe_update_rx_dca(adapter, rx_ring);
+
+#endif
+               r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
+                                     r_idx + 1);
+       }
+
+       if (adapter->itr_setting & 3)
+               ixgbe_set_itr_msix(q_vector);
+#else
+               r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
+                                     r_idx + 1);
+       }
+
+       if (!q_vector->rxr_count)
+               return IRQ_HANDLED;
+
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       rx_ring = &(adapter->rx_ring[r_idx]);
+       /* disable interrupts on this vector only */
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
+       netif_rx_schedule(adapter->netdev, &q_vector->napi);
+#endif
+
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
+{
+       ixgbe_msix_clean_rx(irq, data);
+       ixgbe_msix_clean_tx(irq, data);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_IXGBE_NAPI
+/**
+ * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
+ * @napi: napi struct with our devices info in it
+ * @budget: amount of work driver is allowed to do this pass, in packets
+ *
+ * This function is optimized for cleaning one queue only on a single
+ * q_vector!!!
+ **/
+static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
+{
+       struct ixgbe_q_vector *q_vector =
+                              container_of(napi, struct ixgbe_q_vector, napi);
+       struct ixgbe_adapter *adapter = q_vector->adapter;
+       struct ixgbe_ring *rx_ring = NULL;
+       int work_done = 0;
+       long r_idx;
+
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       rx_ring = &(adapter->rx_ring[r_idx]);
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+       if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+               ixgbe_update_rx_dca(adapter, rx_ring);
+#endif
+
+       ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
+
+       /* If all Rx work done, exit the polling mode */
+       if ((work_done == 0) || !netif_running(adapter->netdev)) {
+               netif_rx_complete(adapter->netdev, napi);
+               if (adapter->itr_setting & 3)
+                       ixgbe_set_itr_msix(q_vector);
+               if (!test_bit(__IXGBE_DOWN, &adapter->state))
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, 
rx_ring->v_idx);
+               return 0;
+       }
+
+       return work_done;
+}
+
+/**
+ * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
+ * @napi: napi struct with our devices info in it
+ * @budget: amount of work driver is allowed to do this pass, in packets
+ *
+ * This function will clean more than one rx queue associated with a
+ * q_vector.
+ **/
+static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
+{
+       struct ixgbe_q_vector *q_vector =
+                              container_of(napi, struct ixgbe_q_vector, napi);
+       struct ixgbe_adapter *adapter = q_vector->adapter;
+       struct ixgbe_ring *rx_ring = NULL;
+       int work_done = 0, i;
+       long r_idx;
+       u16 enable_mask = 0;
+
+       /* attempt to distribute budget to each queue fairly, but don't allow
+        * the budget to go below 1 because we'll exit polling */
+       budget /= (q_vector->rxr_count ?: 1);
+       budget = max(budget, 1);
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       for (i = 0; i < q_vector->rxr_count; i++) {
+               rx_ring = &(adapter->rx_ring[r_idx]);
+#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
+               if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                       ixgbe_update_rx_dca(adapter, rx_ring);
+#endif
+               ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
+               enable_mask |= rx_ring->v_idx;
+               r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
+                                     r_idx + 1);
+       }
+
+       r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+       rx_ring = &(adapter->rx_ring[r_idx]);
+       /* If all Rx work done, exit the polling mode */
+       if ((work_done == 0) || !netif_running(adapter->netdev)) {
+               netif_rx_complete(adapter->netdev, napi);
+               if (adapter->itr_setting & 3)
+                       ixgbe_set_itr_msix(q_vector);
+               if (!test_bit(__IXGBE_DOWN, &adapter->state))
+                       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
+               return 0;
+       }
+
+       return work_done;
+}
+
+#endif /* CONFIG_IXGBE_NAPI */
+static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
+                                     int r_idx)
+{
+       a->q_vector[v_idx].adapter = a;
+       set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
+       a->q_vector[v_idx].rxr_count++;
+       a->rx_ring[r_idx].v_idx = 1 << v_idx;
+
+}
+
+static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
+                                     int r_idx)
+{
+       a->q_vector[v_idx].adapter = a;
+       set_bit(r_idx, a->q_vector[v_idx].txr_idx);
+       a->q_vector[v_idx].txr_count++;
+       a->tx_ring[r_idx].v_idx = 1 << v_idx;
+}
+
+/**
+ * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
+ * @adapter: board private structure to initialize
+ * @vectors: allotted vector count for descriptor rings
+ *
+ * This function maps descriptor rings to the queue-specific vectors
+ * we were allotted through the MSI-X enabling code.  Ideally, we'd have
+ * one vector per ring/queue, but on a constrained vector budget, we
+ * group the rings as "efficiently" as possible.  You would add new
+ * mapping configurations in here.
+ **/
+static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, int 
vectors)
+{
+       int v_start = 0;
+       int rxr_idx = 0, txr_idx = 0;
+       int rxr_remaining = adapter->num_rx_queues;
+       int txr_remaining = adapter->num_tx_queues;
+       int i, j;
+       int rqpv, tqpv;
+       int err = 0;
+
+       /* No mapping required if MSI-X is disabled. */
+       if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
+               goto out;
+
+       /*
+        * The ideal configuration...
+        * We have enough vectors to map one per queue.
+        */
+       if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
+               for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
+                       map_vector_to_rxq(adapter, v_start, rxr_idx);
+
+               for (; txr_idx < txr_remaining; v_start++, txr_idx++)
+                       map_vector_to_txq(adapter, v_start, txr_idx);
+
+               goto out;
+       }
+
+       /*
+        * If we don't have enough vectors for a 1-to-1
+        * mapping, we'll have to group them so there are
+        * multiple queues per vector.
+        */
+       /* Re-adjusting *qpv takes care of the remainder. */
+       for (i = v_start; i < vectors; i++) {
+               rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
+               for (j = 0; j < rqpv; j++) {
+                       map_vector_to_rxq(adapter, i, rxr_idx);
+                       rxr_idx++;
+                       rxr_remaining--;
+               }
+       }
+       for (i = v_start; i < vectors; i++) {
+               tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
+               for (j = 0; j < tqpv; j++) {
+                       map_vector_to_txq(adapter, i, txr_idx);
+                       txr_idx++;
+                       txr_remaining--;
+               }
+       }
+
+out:
+       return err;
+}
+
+/**
+ * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
+ * @adapter: board private structure
+ *
+ * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
+ * interrupts from the kernel.
+ **/
+static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
+{
+       struct net_device *netdev = adapter->netdev;
+       irqreturn_t (*handler)(int, void *);
+       int i, vector, q_vectors, err;
+       int ri = 0, ti = 0;
+
+       /* Decrement for Other and TCP Timer vectors */
+       q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
+
+       /* Map the Tx/Rx rings to the vectors we were allotted. */
+       err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
+       if (err)
+               goto out;
+
+#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
+                         (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
+                         &ixgbe_msix_clean_many)
+       for (vector = 0; vector < q_vectors; vector++) {
+               handler = SET_HANDLER(&adapter->q_vector[vector]);
+
+               if (handler == &ixgbe_msix_clean_rx) {
+                       sprintf(adapter->name[vector], "%s-%s-%d",
+                               netdev->name, "rx", ri++);
+               } else if (handler == &ixgbe_msix_clean_tx) {
+                       sprintf(adapter->name[vector], "%s-%s-%d",
+                               netdev->name, "tx", ti++);
+               } else {
+                       sprintf(adapter->name[vector], "%s-%s-%d",
+                               netdev->name, "TxRx", vector);
+               }
+               err = request_irq(adapter->msix_entries[vector].vector,
+                                 handler, 0, adapter->name[vector],
+                                 &(adapter->q_vector[vector]));
+               if (err) {
+                       DPRINTK(PROBE, ERR,
+                               "request_irq failed for MSIX interrupt "
+                               "Error: %d\n", err);
+                       goto free_queue_irqs;
+               }
+       }
+
+       sprintf(adapter->name[vector], "%s:lsc", netdev->name);
+       err = request_irq(adapter->msix_entries[vector].vector,
+                         &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
+       if (err) {
+               DPRINTK(PROBE, ERR,
+                       "request_irq for msix_lsc failed: %d\n", err);
+               goto free_queue_irqs;
+       }
+
+#ifdef IXGBE_TCP_TIMER
+       vector++;
+       sprintf(adapter->name[vector], "%s:timer", netdev->name);
+       err = request_irq(adapter->msix_entries[vector].vector,
+                         &ixgbe_msix_tcp_timer, 0, adapter->name[vector],
+                         netdev);
+       if (err) {
+               DPRINTK(PROBE, ERR,
+                       "request_irq for msix_tcp_timer failed: %d\n", err);
+               /* Free "Other" interrupt */
+               free_irq(adapter->msix_entries[--vector].vector, netdev);
+               goto free_queue_irqs;
+       }
+
+#endif
+       return 0;
+
+free_queue_irqs:
+       for (i = vector - 1; i >= 0; i--)
+               free_irq(adapter->msix_entries[--vector].vector,
+                        &(adapter->q_vector[i]));
+       adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
+       pci_disable_msix(adapter->pdev);
+       kfree(adapter->msix_entries);
+       adapter->msix_entries = NULL;
+out:
+       return err;
+}
+
+static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       struct ixgbe_q_vector *q_vector = adapter->q_vector;
+       u8 current_itr;
+       u32 new_itr = q_vector->eitr;
+       struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
+       struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
+
+       q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
+                                           q_vector->tx_itr,
+                                           tx_ring->total_packets,
+                                           tx_ring->total_bytes);
+       q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
+                                           q_vector->rx_itr,
+                                           rx_ring->total_packets,
+                                           rx_ring->total_bytes);
+
+       current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
+
+       switch (current_itr) {
+       /* counts and packets in update_itr are dependent on these numbers */
+       case lowest_latency:
+               new_itr = 100000;
+               break;
+       case low_latency:
+               new_itr = 20000; /* aka hwitr = ~200 */
+               break;
+       case bulk_latency:
+               new_itr = 8000;
+               break;
+       default:
+               break;
+       }
+
+       if (new_itr != q_vector->eitr) {
+               u32 itr_reg;
+               /* do an exponential smoothing */
+               new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
+               q_vector->eitr = new_itr;
+               itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
+               /* must write high and low 16 bits to reset counter */
+               IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
+       }
+
+       return;
+}
+
+/**
+ * ixgbe_irq_enable - Enable default interrupt generation settings
+ * @adapter: board private structure
+ **/
+static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
+{
+       u32 mask;
+       mask = IXGBE_EIMS_ENABLE_MASK;
+       if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
+               mask |= IXGBE_EIMS_GPI_SDP1;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
+}
+
+
+/**
+ * ixgbe_intr - legacy mode Interrupt Handler
+ * @irq: interrupt number
+ * @data: pointer to a network interface device structure
+ * @pt_regs: CPU registers structure
+ **/
+static irqreturn_t ixgbe_intr(int irq, void *data)
+{
+       struct net_device *netdev = data;
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 eicr;
+
+       /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
+        * therefore no explict interrupt disable is necessary */
+       eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
+       if (!eicr) {
+#ifdef CONFIG_IXGBE_NAPI
+               /* shared interrupt alert!
+                * make sure interrupts are enabled because the read will
+                * have disabled interrupts due to EIAM */
+               ixgbe_irq_enable(adapter);
+#endif
+               return IRQ_NONE;  /* Not our interrupt */
+       }
+
+       if (eicr & IXGBE_EICR_LSC)
+               ixgbe_check_lsc(adapter);
+
+       ixgbe_check_fan_failure(adapter, eicr);
+
+#ifdef CONFIG_IXGBE_NAPI
+       if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
+               adapter->tx_ring[0].total_packets = 0;
+               adapter->tx_ring[0].total_bytes = 0;
+               adapter->rx_ring[0].total_packets = 0;
+               adapter->rx_ring[0].total_bytes = 0;
+               /* would disable interrupts here but EIAM disabled it */
+               __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
+       }
+
+#else
+       adapter->tx_ring[0].total_packets = 0;
+       adapter->tx_ring[0].total_bytes = 0;
+       adapter->rx_ring[0].total_packets = 0;
+       adapter->rx_ring[0].total_bytes = 0;
+       ixgbe_clean_rx_irq(adapter, adapter->rx_ring);
+       ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
+
+       /* dynamically adjust throttle */
+       if (adapter->itr_setting & 3)
+               ixgbe_set_itr(adapter);
+
+#endif
+       return IRQ_HANDLED;
+}
+
+static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
+{
+       int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
+
+       for (i = 0; i < q_vectors; i++) {
+               struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
+               bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
+               bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
+               q_vector->rxr_count = 0;
+               q_vector->txr_count = 0;
+       }
+}
+
+/**
+ * ixgbe_request_irq - initialize interrupts
+ * @adapter: board private structure
+ *
+ * Attempts to configure interrupts using the best available
+ * capabilities of the hardware and kernel.
+ **/
+static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
+{
+       struct net_device *netdev = adapter->netdev;
+       int err;
+
+       if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
+               err = ixgbe_request_msix_irqs(adapter);
+       } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
+               err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
+                                 netdev->name, netdev);
+       } else {
+               err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
+                                 netdev->name, netdev);
+       }
+
+       if (err)
+               DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
+
+       return err;
+}
+
+static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
+{
+       struct net_device *netdev = adapter->netdev;
+
+       if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
+               int i, q_vectors;
+
+               q_vectors = adapter->num_msix_vectors;
+
+               i = q_vectors - 1;
+#ifdef IXGBE_TCP_TIMER
+               free_irq(adapter->msix_entries[i].vector, netdev);
+               i--;
+#endif
+               free_irq(adapter->msix_entries[i].vector, netdev);
+
+               i--;
+               for (; i >= 0; i--) {
+                       free_irq(adapter->msix_entries[i].vector,
+                                &(adapter->q_vector[i]));
+               }
+
+               ixgbe_reset_q_vectors(adapter);
+       } else {
+               free_irq(adapter->pdev->irq, netdev);
+       }
+}
+
+/**
+ * ixgbe_irq_disable - Mask off interrupt generation on the NIC
+ * @adapter: board private structure
+ **/
+static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
+{
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
+       IXGBE_WRITE_FLUSH(&adapter->hw);
+       if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
+               int i;
+               for (i = 0; i < adapter->num_msix_vectors; i++)
+                       synchronize_irq(adapter->msix_entries[i].vector);
+       } else {
+               synchronize_irq(adapter->pdev->irq);
+       }
+}
+
+static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter)
+{
+       u32 mask = IXGBE_EIMS_RTX_QUEUE;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
+       /* skip the flush */
+}
+
+/**
+ * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
+ *
+ **/
+static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
+                       EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
+
+       ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
+       ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
+
+       map_vector_to_rxq(adapter, 0, 0);
+       map_vector_to_txq(adapter, 0, 0);
+
+       DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
+}
+
+/**
+ * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
+ * @adapter: board private structure
+ *
+ * Configure the Tx unit of the MAC after a reset.
+ **/
+static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
+{
+       u64 tdba, tdwba;
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 i, j, tdlen, txctrl;
+
+       /* Setup the HW Tx Head and Tail descriptor pointers */
+       for (i = 0; i < adapter->num_tx_queues; i++) {
+               struct ixgbe_ring *ring = &adapter->tx_ring[i];
+               j = ring->reg_idx;
+               tdba = ring->dma;
+               tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
+               IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
+                               (tdba & DMA_32BIT_MASK));
+               IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
+               tdwba = ring->dma +
+                       (ring->count * sizeof(union ixgbe_adv_tx_desc));
+               tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
+               IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
+               IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
+               IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
+               IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
+               adapter->tx_ring[i].head = IXGBE_TDH(j);
+               adapter->tx_ring[i].tail = IXGBE_TDT(j);
+               /* Disable Tx Head Writeback RO bit, since this hoses
+                * bookkeeping if things aren't delivered in order.
+                */
+               txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
+               txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+               IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
+       }
+}
+
+#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT        2
+
+static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
+{
+       struct ixgbe_ring *rx_ring;
+       u32 srrctl;
+       int queue0;
+       unsigned long mask;
+
+       /* program one srrctl register per VMDq index */
+       if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
+               long shift, len;
+               mask = (unsigned long) adapter->ring_feature[RING_F_VMDQ].mask;
+               len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
+               shift = find_first_bit(&mask, len);
+               queue0 = (index & mask);
+               index = (index & mask) >> shift;
+       /* if VMDq is not active we must program one srrctl register per
+        * RSS queue since we have enabled RDRXCTL.MVMEN
+        */
+       } else {
+               mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
+               queue0 = index & mask;
+               index = index & mask;
+       }
+
+       rx_ring = &adapter->rx_ring[queue0];
+
+       srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
+
+       srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
+       srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
+
+       if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
+               srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
+               srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
+               srrctl |= ((IXGBE_RX_HDR_SIZE <<
+                           IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
+                          IXGBE_SRRCTL_BSIZEHDR_MASK);
+       } else {
+               srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
+
+               if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
+                       srrctl |= IXGBE_RXBUFFER_2048 >>
+                                 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
+               else
+                       srrctl |= rx_ring->rx_buf_len >>
+                                 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
+       }
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
+}
+
+#ifndef IXGBE_NO_INET_LRO
+/**
+ * ixgbe_get_skb_hdr - helper function for LRO header processing
+ * @skb: pointer to sk_buff to be added to LRO packet
+ * @iphdr: pointer to ip header structure
+ * @tcph: pointer to tcp header structure
+ * @hdr_flags: pointer to header flags
+ * @priv: private data
+ **/
+static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
+                             u64 *hdr_flags, void *priv)
+{
+       union ixgbe_adv_rx_desc *rx_desc = priv;
+
+       /* Verify that this is a valid IPv4 TCP packet */
+       if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
+            (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
+               return -1;
+
+       /* Set network headers */
+       skb_reset_network_header(skb);
+       skb_set_transport_header(skb, ip_hdrlen(skb));
+       *iphdr = ip_hdr(skb);
+       *tcph = tcp_hdr(skb);
+       *hdr_flags = LRO_IPV4 | LRO_TCP;
+       return 0;
+}
+
+#endif /* IXGBE_NO_INET_LRO */
+/**
+ * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
+ * @adapter: board private structure
+ *
+ * Configure the Rx unit of the MAC after a reset.
+ **/
+static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
+{
+       u64 rdba;
+       struct ixgbe_hw *hw = &adapter->hw;
+       struct net_device *netdev = adapter->netdev;
+       int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
+       int i, j;
+       u32 rdlen, rxctrl, rxcsum;
+       static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
+                         0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
+                         0x6A3E67EA, 0x14364D17, 0x3BED200D};
+       u32 fctrl, hlreg0;
+       u32 reta = 0, mrqc;
+       u32 vmdctl;
+       u32 rdrxctl;
+       int rx_buf_len;
+
+#ifndef IXGBE_NO_LRO
+       adapter->lro_data.max = lromax;
+
+       if (lromax * netdev->mtu > (1 << 16))
+               adapter->lro_data.max = ((1 << 16) / netdev->mtu) - 1;
+
+#endif
+       /* Decide whether to use packet split mode or not */
+       if (netdev->mtu > ETH_DATA_LEN) {
+               if (adapter->flags & IXGBE_FLAG_RX_PS_CAPABLE)
+                       adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
+               else
+                       adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
+       } else {
+               if (adapter->flags & IXGBE_FLAG_RX_1BUF_CAPABLE) {
+                       adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
+               } else
+                       adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
+       }
+
+       /* Set the RX buffer length according to the mode */
+       if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
+               rx_buf_len = IXGBE_RX_HDR_SIZE;
+       } else {
+               if (netdev->mtu <= ETH_DATA_LEN)
+                       rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
+               else
+                       rx_buf_len = ALIGN(max_frame, 1024);
+       }
+
+       fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
+       fctrl |= IXGBE_FCTRL_BAM;
+       fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
+       fctrl |= IXGBE_FCTRL_PMCF;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
+
+       hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
+       if (adapter->netdev->mtu <= ETH_DATA_LEN)
+               hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
+       else
+               hlreg0 |= IXGBE_HLREG0_JUMBOEN;
+       IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
+
+       rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
+       /* disable receives while setting up the descriptors */
+       rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
+       IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
+
+       /* Setup the HW Rx Head and Tail Descriptor Pointers and
+        * the Base and Length of the Rx Descriptor Ring */
+       for (i = 0; i < adapter->num_rx_queues; i++) {
+               rdba = adapter->rx_ring[i].dma;
+               j = adapter->rx_ring[i].reg_idx;
+               IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
+               IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
+               IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
+               IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
+               IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
+               adapter->rx_ring[i].head = IXGBE_RDH(j);
+               adapter->rx_ring[i].tail = IXGBE_RDT(j);
+               if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
+                       /* Reserve VMDq set 1 for FCoE, using 3k buffers */
+                       if ((i & adapter->ring_feature[RING_F_VMDQ].mask) == 1)
+                               adapter->rx_ring[i].rx_buf_len = 3072;
+                       else
+                               adapter->rx_ring[i].rx_buf_len = rx_buf_len;
+               } else {
+                       adapter->rx_ring[i].rx_buf_len = rx_buf_len;
+               }
+#ifndef IXGBE_NO_INET_LRO
+               /* Intitial LRO Settings */
+               adapter->rx_ring[i].lro_mgr.max_aggr = adapter->lro_max_aggr;
+               adapter->rx_ring[i].lro_mgr.max_desc = 
IXGBE_MAX_LRO_DESCRIPTORS;
+               adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
+               adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
+#ifdef CONFIG_IXGBE_NAPI
+               if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
+                       adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
+#endif
+               adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
+               adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
+               adapter->rx_ring[i].lro_mgr.ip_summed_aggr = 
CHECKSUM_UNNECESSARY;
+
+#endif
+               ixgbe_configure_srrctl(adapter, j);
+       }
+
+       /*
+        * For VMDq support of different descriptor types or
+        * buffer sizes through the use of multiple SRRCTL
+        * registers, RDRXCTL.MVMEN must be set to 1
+        *
+        * also, the manual doesn't mention it clearly but DCA hints
+        * will only use queue 0's tags unless this bit is set.  Side
+        * effects of setting this bit are only that SRRCTL must be
+        * fully programmed [0..15]
+        */
+       rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
+       rdrxctl |= IXGBE_RDRXCTL_MVMEN;
+       IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
+
+       if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
+               IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
+               vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
+               IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL,
+                               vmdctl | IXGBE_VMD_CTL_VMDQ_EN);
+       }
+
+       if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
+               /* Fill out redirection table */
+               for (i = 0, j = 0; i < 128; i++, j++) {
+                       if (j == adapter->ring_feature[RING_F_RSS].indices)
+                               j = 0;
+                       /* reta = 4-byte sliding window of
+                        * 0x00..(indices-1)(indices-1)00..etc. */
+                       reta = (reta << 8) | (j * 0x11);
+                       if ((i & 3) == 3)
+                               IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
+               }
+
+               /* Fill out hash function seeds */
+               for (i = 0; i < 10; i++)
+                       IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
+
+               mrqc = IXGBE_MRQC_RSSEN
+                   /* Perform hash on these packet types */
+                      | IXGBE_MRQC_RSS_FIELD_IPV4
+                      | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
+                      | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
+                      | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
+                      | IXGBE_MRQC_RSS_FIELD_IPV6_EX
+                      | IXGBE_MRQC_RSS_FIELD_IPV6
+                      | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
+                      | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
+                      | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
+               IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
+       }
+
+       rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
+
+       if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
+           adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
+               /* Disable indicating checksum in descriptor, enables
+                * RSS hash */
+               rxcsum |= IXGBE_RXCSUM_PCSD;
+       }
+       if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
+               /* Enable IPv4 payload checksum for UDP fragments
+                * if PCSD is not set */
+               rxcsum |= IXGBE_RXCSUM_IPPCSE;
+       }
+
+       IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
+}
+
+#ifdef NETIF_F_HW_VLAN_TX
+static void ixgbe_vlan_rx_register(struct net_device *netdev,
+                                   struct vlan_group *grp)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       u32 ctrl;
+
+       if (!test_bit(__IXGBE_DOWN, &adapter->state))
+               ixgbe_irq_disable(adapter);
+       adapter->vlgrp = grp;
+
+       /*
+        * For a DCB driver, always enable VLAN tag stripping so we can
+        * still receive traffic from a DCB-enabled host.
+        */
+       ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
+       ctrl |= IXGBE_VLNCTRL_VME;
+       ctrl &= ~IXGBE_VLNCTRL_CFIEN;
+       IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
+
+       if (grp) {
+               /* enable VLAN tag insert/strip */
+               ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
+               ctrl |= IXGBE_VLNCTRL_VME;
+               ctrl &= ~IXGBE_VLNCTRL_CFIEN;
+               IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
+       }
+
+       if (!test_bit(__IXGBE_DOWN, &adapter->state))
+               ixgbe_irq_enable(adapter);
+}
+
+static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+#ifndef HAVE_NETDEV_VLAN_FEATURES
+       struct net_device *v_netdev;
+#endif /* HAVE_NETDEV_VLAN_FEATURES */
+
+       /* add VID to filter table */
+       if (hw->mac.ops.set_vfta)
+               hw->mac.ops.set_vfta(hw, vid, 0, true);
+#ifndef HAVE_NETDEV_VLAN_FEATURES
+       /*
+        * Copy feature flags from netdev to the vlan netdev for this vid.
+        * This allows things like TSO to bubble down to our vlan device.
+        */
+       v_netdev = vlan_group_get_device(adapter->vlgrp, vid);
+       v_netdev->features |= adapter->netdev->features;
+       vlan_group_set_device(adapter->vlgrp, vid, v_netdev);
+#endif /* HAVE_NETDEV_VLAN_FEATURES */
+}
+
+static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
+{
+       struct ixgbe_adapter *adapter = netdev_priv(netdev);
+       struct ixgbe_hw *hw = &adapter->hw;
+
+       if (!test_bit(__IXGBE_DOWN, &adapter->state))
+               ixgbe_irq_disable(adapter);
+
+       vlan_group_set_device(adapter->vlgrp, vid, NULL);
+
+       if (!test_bit(__IXGBE_DOWN, &adapter->state))
+               ixgbe_irq_enable(adapter);
+       /* remove VID from filter table */
+       if (hw->mac.ops.set_vfta)
+               hw->mac.ops.set_vfta(hw, vid, 0, false);
+}
+
+static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
+{
+       ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
+
+       if (adapter->vlgrp) {
+               u16 vid;
+               for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
+                       if (!vlan_group_get_device(adapter->vlgrp, vid))
+                               continue;
+                       ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
+               }
+       }
+}
+
+#endif
+/**
+ * compare_ether_oui - Compare two OUIs
+ * @addr1: pointer to a 6 byte array containing an Ethernet address
+ * @addr2: pointer to a 6 byte array containing an Ethernet address
+ *
+ * Compare the Organizationally Unique Identifiers from two Ethernet addresses,
+ * returns 0 if equal
+ */
+static inline int compare_ether_oui(const u8 *a, const u8 *b)
+{
+       return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;
+}
+
+/**
+ * is_fcoe_ether_addr - Compare an Ethernet address to FCoE OUI
+ * @addr1: pointer to a 6 byte array containing an Ethernet address
+ * @addr2: pointer to a 6 byte array containing an Ethernet address
+ *
+ * Compare the Organizationally Unique Identifier from an Ethernet addresses
+ * with the well known Fibre Channel over Ethernet OUI
+ *
+ * Returns 1 if the address has an FCoE OUI
+ */
+static inline int is_fcoe_ether_addr(const u8 *addr)
+{
+       static const u8 fcoe_oui[] = { 0x0e, 0xfc, 0x00 };
+       return compare_ether_oui(addr, fcoe_oui) == 0;
+}
+
+static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 
*vmdq)
+{
+       struct ixgbe_adapter *adapter = hw->back;
+       struct dev_mc_list *mc_ptr;
+       u8 *addr = *mc_addr_ptr;
+       *vmdq = 0;
+
+       mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
+       if (mc_ptr->next)
+               *mc_addr_ptr = mc_ptr->next->dmi_addr;
+       else
+               *mc_addr_ptr = NULL;
+
+       if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
+               /* VMDQ set 1 is used for FCoE */

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