[Xen-changelog] [xen-unstable] xend: fixup the Secondary Bus Reset.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1223888916 -3600
# Node ID 98d5370fec1a1f8438a62b51117207f1d40b8256
# Parent  0d1875d2e5f215eb35bc6234ca382ce5be672ae1
xend: fixup the Secondary Bus Reset.

Use the read-modify-write operation.
Change the wrong 'I' to a correct 'H'.

Signed-off-by: Dexuan Cui <dexuan.cui@xxxxxxxxx>
---
 tools/python/xen/util/pci.py |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff -r 0d1875d2e5f2 -r 98d5370fec1a tools/python/xen/util/pci.py
--- a/tools/python/xen/util/pci.py      Mon Oct 13 10:08:16 2008 +0100
+++ b/tools/python/xen/util/pci.py      Mon Oct 13 10:08:36 2008 +0100
@@ -476,15 +476,16 @@ class PciDevice:
         parent_path = sysfs_mnt + SYSFS_PCI_DEVS_PATH + '/' + \
             target_bus + SYSFS_PCI_DEV_CONFIG_PATH
         fd = os.open(parent_path, os.O_RDWR)
-        # Save state of bridge control register - restore after reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
         br_cntl = (struct.unpack('H', os.read(fd, 2)))[0]
         # Assert Secondary Bus Reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
-        os.write(fd, struct.pack('I', PCI_BRIDGE_CTL_BUS_RESET))
+        br_cntl |= PCI_BRIDGE_CTL_BUS_RESET
+        os.write(fd, struct.pack('H', br_cntl))
         time.sleep(0.200)
         # De-assert Secondary Bus Reset
         os.lseek(fd, PCI_CB_BRIDGE_CONTROL, 0)
+        br_cntl &= ~PCI_BRIDGE_CTL_BUS_RESET
         os.write(fd, struct.pack('H', br_cntl))
         time.sleep(0.200)
         os.close(fd)

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