# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1215600165 -3600
# Node ID be20b11656bb706f5e684df1ada239116c92cdb1
# Parent af555a012e67f9f4e2b6558e8caddf32f33a7b38
Some latest Intel CPU models support cpuid feature mask.
CPUID.1.EAX>0x00010674.CPUID mask feature is intended to be used to
limit the feature flags reported by CPUID.1.EDX:ECX.
Signed-off-by: Liping Ke <liping.ke@xxxxxxxxx>
Signed-off-by: Jun Nakajima <nakajima.jun@xxxxxxxxx>
Signed-off-by: Yunhong Jiang <yunhong.jiang@xxxxxxxxx>
Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
---
xen/arch/x86/cpu/intel.c | 31 +++++++++++++++++++++++++++++++
xen/include/asm-x86/msr-index.h | 3 +++
2 files changed, 34 insertions(+)
diff -r af555a012e67 -r be20b11656bb xen/arch/x86/cpu/intel.c
--- a/xen/arch/x86/cpu/intel.c Wed Jul 09 11:05:26 2008 +0100
+++ b/xen/arch/x86/cpu/intel.c Wed Jul 09 11:42:45 2008 +0100
@@ -18,12 +18,41 @@
extern int trap_init_f00f_bug(void);
+/*
+ * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
+ * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
+ * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
+ * 'rev down' to E8400, you can set these values in these Xen boot parameters.
+ */
+static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
+integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
+integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
+
#ifdef CONFIG_X86_INTEL_USERCOPY
/*
* Alignment at which movsl is preferred for bulk memory copies.
*/
struct movsl_mask movsl_mask __read_mostly;
#endif
+
+static void __devinit set_cpuidmask(void)
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
+ return;
+
+ cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
+ if (eax < 0x00010674) {
+ printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
+ smp_processor_id());
+ return;
+ }
+
+ wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
+ opt_cpuid_mask_ecx ? : ~0u,
+ opt_cpuid_mask_edx ? : ~0u);
+}
void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
{
@@ -158,6 +187,8 @@ static void __devinit init_intel(struct
detect_ht(c);
+ set_cpuidmask();
+
/* Work around errata */
Intel_errata_workarounds(c);
diff -r af555a012e67 -r be20b11656bb xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Wed Jul 09 11:05:26 2008 +0100
+++ b/xen/include/asm-x86/msr-index.h Wed Jul 09 11:42:45 2008 +0100
@@ -122,6 +122,9 @@
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186
#define MSR_P6_EVNTSEL1 0x00000187
+
+/* MSR for cpuid feature mask */
+#define MSR_IA32_CPUID_FEATURE_MASK1 0x00000478
/* MSRs & bits used for VMX enabling */
#define MSR_IA32_VMX_BASIC 0x480
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