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[Xen-changelog] [xen-3.1-testing] vmx: On EPT-enabled Intel CPUs we must

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Subject: [Xen-changelog] [xen-3.1-testing] vmx: On EPT-enabled Intel CPUs we must explicitly request CR3 load and
From: "Xen patchbot-3.1-testing" <patchbot-3.1-testing@xxxxxxxxxxxxxxxxxxx>
Date: Wed, 09 Apr 2008 09:10:39 -0700
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# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1207749625 -3600
# Node ID a5f7058a959f8597a809350f37aae00086da3ac6
# Parent  ae5afeac62794ea66232a4b8b961d654d3808826
vmx: On EPT-enabled Intel CPUs we must explicitly request CR3 load and
store intercepts.

Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vmcs.c        |    2 ++
 xen/include/asm-x86/hvm/vmx/vmcs.h |    2 ++
 2 files changed, 4 insertions(+)

diff -r ae5afeac6279 -r a5f7058a959f xen/arch/x86/hvm/vmx/vmcs.c
--- a/xen/arch/x86/hvm/vmx/vmcs.c       Wed Apr 09 13:33:35 2008 +0100
+++ b/xen/arch/x86/hvm/vmx/vmcs.c       Wed Apr 09 15:00:25 2008 +0100
@@ -80,6 +80,8 @@ void vmx_init_vmcs_config(void)
 
     min = (CPU_BASED_HLT_EXITING |
            CPU_BASED_INVLPG_EXITING |
+           CPU_BASED_CR3_LOAD_EXITING |
+           CPU_BASED_CR3_STORE_EXITING |
            CPU_BASED_MONITOR_EXITING |
            CPU_BASED_MWAIT_EXITING |
            CPU_BASED_MOV_DR_EXITING |
diff -r ae5afeac6279 -r a5f7058a959f xen/include/asm-x86/hvm/vmx/vmcs.h
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h        Wed Apr 09 13:33:35 2008 +0100
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h        Wed Apr 09 15:00:25 2008 +0100
@@ -101,6 +101,8 @@ void vmx_vmcs_exit(struct vcpu *v);
 #define CPU_BASED_MWAIT_EXITING               0x00000400
 #define CPU_BASED_RDPMC_EXITING               0x00000800
 #define CPU_BASED_RDTSC_EXITING               0x00001000
+#define CPU_BASED_CR3_LOAD_EXITING            0x00008000
+#define CPU_BASED_CR3_STORE_EXITING           0x00010000
 #define CPU_BASED_CR8_LOAD_EXITING            0x00080000
 #define CPU_BASED_CR8_STORE_EXITING           0x00100000
 #define CPU_BASED_TPR_SHADOW                  0x00200000

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