# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1206015108 0
# Node ID 483c882a7df1a3fe81b036fc2f1777a35a6c5ac5
# Parent 3479b64a514f1013bcd1d47e7a391bf24563d45c
x86: fix feature availability for PV guests
PV guests should not be allowed to believe features not currently
virtualized (in many cases, requiring special MSRs) are available. Of
course it is bad enough that to work on older hypervisors guests will
still need to special case this, but better fix it now than never.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
xen-unstable changeset: 17238:4b157affc08f75cb0e2d69954357cfb1630e798c
xen-unstable date: Tue Mar 18 16:05:24 2008 +0000
---
xen/arch/x86/traps.c | 76 ++++++++++++++++++++++++++++++++-------
xen/include/asm-x86/cpufeature.h | 4 ++
xen/include/asm-x86/msr-index.h | 2 +
3 files changed, 70 insertions(+), 12 deletions(-)
diff -r 3479b64a514f -r 483c882a7df1 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Thu Mar 20 12:11:08 2008 +0000
+++ b/xen/arch/x86/traps.c Thu Mar 20 12:11:48 2008 +0000
@@ -674,32 +674,75 @@ static int emulate_forced_invalid_op(str
: "=a" (a), "=b" (b), "=c" (c), "=d" (d)
: "0" (a), "1" (b), "2" (c), "3" (d) );
- if ( regs->eax == 1 )
+ if ( (regs->eax & 0x7fffffff) == 1 )
{
/* Modify Feature Information. */
__clear_bit(X86_FEATURE_VME, &d);
__clear_bit(X86_FEATURE_PSE, &d);
__clear_bit(X86_FEATURE_PGE, &d);
+ __clear_bit(X86_FEATURE_MCE, &d);
+ __clear_bit(X86_FEATURE_MCA, &d);
+ if ( !IS_PRIV(current->domain) )
+ __clear_bit(X86_FEATURE_MTRR, &d);
+ __clear_bit(X86_FEATURE_PSE36, &d);
+ }
+ switch ( (uint32_t)regs->eax )
+ {
+ case 1:
+ /* Modify Feature Information. */
if ( !cpu_has_sep )
__clear_bit(X86_FEATURE_SEP, &d);
#ifdef __i386__
if ( !supervisor_mode_kernel )
__clear_bit(X86_FEATURE_SEP, &d);
#endif
- if ( !IS_PRIV(current->domain) )
- __clear_bit(X86_FEATURE_MTRR, &d);
- }
- else if ( regs->eax == 0x80000001 )
- {
+ __clear_bit(X86_FEATURE_DS, &d);
+ __clear_bit(X86_FEATURE_ACC, &d);
+ __clear_bit(X86_FEATURE_PBE, &d);
+
+ __clear_bit(X86_FEATURE_DTES64 % 32, &c);
+ __clear_bit(X86_FEATURE_MWAIT % 32, &c);
+ __clear_bit(X86_FEATURE_DSCPL % 32, &c);
+ __clear_bit(X86_FEATURE_VMXE % 32, &c);
+ __clear_bit(X86_FEATURE_SMXE % 32, &c);
+ __clear_bit(X86_FEATURE_EST % 32, &c);
+ __clear_bit(X86_FEATURE_TM2 % 32, &c);
+ if ( is_pv_32bit_vcpu(current) )
+ __clear_bit(X86_FEATURE_CX16 % 32, &c);
+ __clear_bit(X86_FEATURE_XTPR % 32, &c);
+ __clear_bit(X86_FEATURE_PDCM % 32, &c);
+ __clear_bit(X86_FEATURE_DCA % 32, &c);
+ break;
+ case 0x80000001:
/* Modify Feature Information. */
-#ifdef __i386__
- __clear_bit(X86_FEATURE_SYSCALL % 32, &d);
-#endif
+ if ( is_pv_32bit_vcpu(current) )
+ {
+ __clear_bit(X86_FEATURE_LM % 32, &d);
+ __clear_bit(X86_FEATURE_LAHF_LM % 32, &c);
+ }
+#ifndef __i386__
+ if ( is_pv_32on64_vcpu(current) &&
+ boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+#endif
+ __clear_bit(X86_FEATURE_SYSCALL % 32, &d);
+ __clear_bit(X86_FEATURE_PAGE1GB % 32, &d);
__clear_bit(X86_FEATURE_RDTSCP % 32, &d);
- }
- else
- {
+
+ __clear_bit(X86_FEATURE_SVME % 32, &c);
+ __clear_bit(X86_FEATURE_OSVW % 32, &c);
+ __clear_bit(X86_FEATURE_IBS % 32, &c);
+ __clear_bit(X86_FEATURE_SKINIT % 32, &c);
+ __clear_bit(X86_FEATURE_WDT % 32, &c);
+ break;
+ case 5: /* MONITOR/MWAIT */
+ case 0xa: /* Architectural Performance Monitor Features */
+ case 0x8000000a: /* SVM revision and features */
+ case 0x8000001b: /* Instruction Based Sampling */
+ a = b = c = d = 0;
+ break;
+ default:
(void)cpuid_hypervisor_leaves(regs->eax, &a, &b, &c, &d);
+ break;
}
regs->eax = a;
@@ -2007,6 +2050,15 @@ static int emulate_privileged_op(struct
case MSR_EFER:
if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
goto fail;
+ break;
+ case MSR_IA32_MISC_ENABLE:
+ if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
+ goto fail;
+ regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL |
+ MSR_IA32_MISC_ENABLE_MONITOR_ENABLE);
+ regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
+ MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
+ MSR_IA32_MISC_ENABLE_XTPR_DISABLE;
break;
default:
if ( rdmsr_hypervisor_regs(regs->ecx, &l, &h) )
diff -r 3479b64a514f -r 483c882a7df1 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Thu Mar 20 12:11:08 2008 +0000
+++ b/xen/include/asm-x86/cpufeature.h Thu Mar 20 12:11:48 2008 +0000
@@ -42,6 +42,7 @@
#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
+#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
/* Don't duplicate feature flags which are redundant with Intel! */
@@ -76,6 +77,7 @@
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
+#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
#define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
@@ -115,6 +117,8 @@
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */
#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based
Sampling */
+#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
diff -r 3479b64a514f -r 483c882a7df1 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Thu Mar 20 12:11:08 2008 +0000
+++ b/xen/include/asm-x86/msr-index.h Thu Mar 20 12:11:48 2008 +0000
@@ -255,6 +255,8 @@
#define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
+#define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
+#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
/* Intel Model 6 */
#define MSR_P6_EVNTSEL0 0x00000186
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