# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1197910266 25200
# Node ID 213a7029fdbcae0a97c1b5d921551fbc71b4dcbe
# Parent 57eec263d48be4bf3d7dac217f1b9a0b5042f97a
[IA64] xenoprof: don't modify mPSR.pp. PV case
Don't change mPSR.pp for xenoprof for PV domain case.
xenoprof manages mPSR.pp so that mPSR.pp shouldn't be modified.
Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
---
xen/arch/ia64/xen/hyperprivop.S | 17 ++++++++++++-----
xen/arch/ia64/xen/vcpu.c | 34 +++++++++++++++++++++++++++-------
2 files changed, 39 insertions(+), 12 deletions(-)
diff -r 57eec263d48b -r 213a7029fdbc xen/arch/ia64/xen/hyperprivop.S
--- a/xen/arch/ia64/xen/hyperprivop.S Mon Dec 17 09:45:53 2007 -0700
+++ b/xen/arch/ia64/xen/hyperprivop.S Mon Dec 17 09:51:06 2007 -0700
@@ -1099,14 +1099,21 @@ just_do_rfi:
// force on psr.ic, i, dt, rt, it, bn
movl r20=(IA64_PSR_I|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT| \
IA64_PSR_IT|IA64_PSR_BN)
+ // keep cr.ipsr.pp and set vPSR.pp = vIPSR.pp
+ mov r22=cr.ipsr
;;
or r21=r21,r20
+ tbit.z p10,p11 = r22, IA64_PSR_PP_BIT
;;
adds r20=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
tbit.z p8,p9 = r21, IA64_PSR_DFH_BIT
+ adds r23=XSI_VPSR_PP_OFS-XSI_PSR_IC_OFS,r18
;;
(p9) mov r27=1;;
(p9) st1 [r20]=r27
+ dep r21=r22,r21,IA64_PSR_PP_BIT,1
+ (p10) st1 [r23]=r0
+ (p11) st1 [r23]=r27
;;
(p8) st1 [r20]=r0
(p8) adds r20=XSI_HPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
@@ -1484,20 +1491,20 @@ ENTRY(hyper_get_psr)
movl r8=0xffffffff | IA64_PSR_MC | IA64_PSR_IT;;
// only return PSR{36:35,31:0}
and r8=r8,r24
- // set vpsr.ic
+ // get vpsr.ic
ld4 r21=[r18];;
dep r8=r21,r8,IA64_PSR_IC_BIT,1
- // set vpsr.pp
+ // get vpsr.pp
adds r20=XSI_VPSR_PP_OFS-XSI_PSR_IC_OFS,r18 ;;
ld1 r21=[r20];;
dep r8=r21,r8,IA64_PSR_PP_BIT,1
- // set vpsr.dt
+ // get vpsr.dt
adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
ld4 r21=[r20];;
cmp.ne p6,p0=r21,r0
;;
(p6) dep.z r8=r8,IA64_PSR_DT_BIT,1
- // set vpsr.i
+ // get vpsr.i
adds r20=XSI_PSR_I_ADDR_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r20=[r20];;
ld1 r21=[r20];;
@@ -1505,7 +1512,7 @@ ENTRY(hyper_get_psr)
;;
(p8) dep r8=-1,r8,IA64_PSR_I_BIT,1
(p9) dep r8=0,r8,IA64_PSR_I_BIT,1
- // set vpsr.dfh
+ // get vpsr.dfh
adds r20=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
ld1 r21=[r20];;
dep r8=r21,r8,IA64_PSR_DFH_BIT,1
diff -r 57eec263d48b -r 213a7029fdbc xen/arch/ia64/xen/vcpu.c
--- a/xen/arch/ia64/xen/vcpu.c Mon Dec 17 09:45:53 2007 -0700
+++ b/xen/arch/ia64/xen/vcpu.c Mon Dec 17 09:51:06 2007 -0700
@@ -329,8 +329,11 @@ IA64FAULT vcpu_reset_psr_sm(VCPU * vcpu,
if (imm.dfl)
ipsr->dfl = 0;
if (imm.pp) {
- ipsr->pp = 1;
- psr.pp = 1; // priv perf ctrs always enabled
+ // xenoprof:
+ // Don't change psr.pp and ipsr->pp
+ // They are manipulated by xenoprof
+ // psr.pp = 1;
+ // ipsr->pp = 1;
PSCB(vcpu, vpsr_pp) = 0; // but fool the domain if it gets psr
}
if (imm.up) {
@@ -391,8 +394,11 @@ IA64FAULT vcpu_set_psr_sm(VCPU * vcpu, u
if (imm.dfl)
ipsr->dfl = 1;
if (imm.pp) {
- ipsr->pp = 1;
- psr.pp = 1;
+ // xenoprof:
+ // Don't change psr.pp and ipsr->pp
+ // They are manipulated by xenoprof
+ // psr.pp = 1;
+ // ipsr->pp = 1;
PSCB(vcpu, vpsr_pp) = 1;
}
if (imm.sp) {
@@ -462,10 +468,16 @@ IA64FAULT vcpu_set_psr_l(VCPU * vcpu, u6
if (newpsr.dfl)
ipsr->dfl = 1;
if (newpsr.pp) {
- ipsr->pp = 1;
+ // xenoprof:
+ // Don't change ipsr->pp
+ // It is manipulated by xenoprof
+ // ipsr->pp = 1;
PSCB(vcpu, vpsr_pp) = 1;
} else {
- ipsr->pp = 1;
+ // xenoprof:
+ // Don't change ipsr->pp
+ // It is manipulated by xenoprof
+ // ipsr->pp = 1;
PSCB(vcpu, vpsr_pp) = 0;
}
if (newpsr.up)
@@ -517,7 +529,15 @@ IA64FAULT vcpu_set_psr(VCPU * vcpu, u64
newpsr.val |= IA64_PSR_DI;
newpsr.val |= IA64_PSR_I | IA64_PSR_IC | IA64_PSR_DT | IA64_PSR_RT |
- IA64_PSR_IT | IA64_PSR_BN | IA64_PSR_DI | IA64_PSR_PP;
+ IA64_PSR_IT | IA64_PSR_BN | IA64_PSR_DI;
+ /*
+ * xenoprof:
+ * keep psr.pp unchanged for xenoprof.
+ */
+ if (regs->cr_ipsr & IA64_PSR_PP)
+ newpsr.val |= IA64_PSR_PP;
+ else
+ newpsr.val &= ~IA64_PSR_PP;
vpsr.val = val;
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