# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1197455118 0
# Node ID 5a451d2c36bcb21f9b5a4098d66ed6815a762162
# Parent 8ae3f083490a804ca1ae4b5b9463a418e1a7e71a
hvm: MTRR MSRs save/restore support.
Signed-off-by: Disheng Su <disheng.su@xxxxxxxxx>
---
xen/arch/x86/hvm/mtrr.c | 80 +++++++++++++++++++++++++++++++++
xen/include/asm-x86/mtrr.h | 1
xen/include/public/arch-x86/hvm/save.h | 19 +++++++
3 files changed, 99 insertions(+), 1 deletion(-)
diff -r 8ae3f083490a -r 5a451d2c36bc xen/arch/x86/hvm/mtrr.c
--- a/xen/arch/x86/hvm/mtrr.c Wed Dec 12 10:22:39 2007 +0000
+++ b/xen/arch/x86/hvm/mtrr.c Wed Dec 12 10:25:18 2007 +0000
@@ -769,3 +769,83 @@ int32_t hvm_set_mem_pinned_cacheattr(
return 0;
}
+
+static int hvm_save_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
+{
+ int i;
+ struct vcpu *v;
+ struct hvm_hw_mtrr hw_mtrr;
+ struct mtrr_state *mtrr_state;
+ /* save mtrr&pat */
+ for_each_vcpu(d, v)
+ {
+ mtrr_state = &v->arch.hvm_vcpu.mtrr;
+
+ hw_mtrr.msr_pat_cr = v->arch.hvm_vcpu.pat_cr;
+
+ hw_mtrr.msr_mtrr_def_type = mtrr_state->def_type
+ | (mtrr_state->enabled << 10);
+ hw_mtrr.msr_mtrr_cap = mtrr_state->mtrr_cap;
+
+ for ( i = 0; i < MTRR_VCNT; i++ )
+ {
+ /* save physbase */
+ hw_mtrr.msr_mtrr_var[i*2] =
+ ((uint64_t*)mtrr_state->var_ranges)[i*2];
+ /* save physmask */
+ hw_mtrr.msr_mtrr_var[i*2+1] =
+ ((uint64_t*)mtrr_state->var_ranges)[i*2+1];
+ }
+
+ for ( i = 0; i < NUM_FIXED_MSR; i++ )
+ hw_mtrr.msr_mtrr_fixed[i] =
+ ((uint64_t*)mtrr_state->fixed_ranges)[i];
+
+ if ( hvm_save_entry(MTRR, v->vcpu_id, h, &hw_mtrr) != 0 )
+ return 1;
+ }
+ return 0;
+}
+
+static int hvm_load_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
+{
+ int vcpuid, i;
+ struct vcpu *v;
+ struct mtrr_state *mtrr_state;
+ struct hvm_hw_mtrr hw_mtrr;
+
+ vcpuid = hvm_load_instance(h);
+ if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
+ {
+ gdprintk(XENLOG_ERR, "HVM restore: domain has no vcpu %u\n", vcpuid);
+ return -EINVAL;
+ }
+
+ if ( hvm_load_entry(MTRR, h, &hw_mtrr) != 0 )
+ return -EINVAL;
+
+ mtrr_state = &v->arch.hvm_vcpu.mtrr;
+
+ pat_msr_set(&v->arch.hvm_vcpu.pat_cr, hw_mtrr.msr_pat_cr);
+
+ mtrr_state->mtrr_cap = hw_mtrr.msr_mtrr_cap;
+
+ for ( i = 0; i < NUM_FIXED_MSR; i++ )
+ mtrr_fix_range_msr_set(mtrr_state, i, hw_mtrr.msr_mtrr_fixed[i]);
+
+ for ( i = 0; i < MTRR_VCNT; i++ )
+ {
+ mtrr_var_range_msr_set(mtrr_state,
+ MTRRphysBase_MSR(i), hw_mtrr.msr_mtrr_var[i*2]);
+ mtrr_var_range_msr_set(mtrr_state,
+ MTRRphysMask_MSR(i), hw_mtrr.msr_mtrr_var[i*2+1]);
+ }
+
+ mtrr_def_type_msr_set(mtrr_state, hw_mtrr.msr_mtrr_def_type);
+
+ v->arch.hvm_vcpu.mtrr.is_initialized = 1;
+ return 0;
+}
+
+HVM_REGISTER_SAVE_RESTORE(MTRR, hvm_save_mtrr_msr, hvm_load_mtrr_msr,
+ 1, HVMSR_PER_VCPU);
diff -r 8ae3f083490a -r 5a451d2c36bc xen/include/asm-x86/mtrr.h
--- a/xen/include/asm-x86/mtrr.h Wed Dec 12 10:22:39 2007 +0000
+++ b/xen/include/asm-x86/mtrr.h Wed Dec 12 10:25:18 2007 +0000
@@ -47,6 +47,7 @@ struct mtrr_var_range {
};
#define NUM_FIXED_RANGES 88
+#define NUM_FIXED_MSR 11
struct mtrr_state {
struct mtrr_var_range *var_ranges;
mtrr_type fixed_ranges[NUM_FIXED_RANGES];
diff -r 8ae3f083490a -r 5a451d2c36bc xen/include/public/arch-x86/hvm/save.h
--- a/xen/include/public/arch-x86/hvm/save.h Wed Dec 12 10:22:39 2007 +0000
+++ b/xen/include/public/arch-x86/hvm/save.h Wed Dec 12 10:25:18 2007 +0000
@@ -405,9 +405,26 @@ struct hvm_hw_pmtimer {
DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
+/*
+ * MTRR MSRs
+ */
+
+struct hvm_hw_mtrr {
+#define MTRR_VCNT 8
+#define NUM_FIXED_MSR 11
+ uint64_t msr_pat_cr;
+ /* mtrr physbase & physmask msr pair*/
+ uint64_t msr_mtrr_var[MTRR_VCNT*2];
+ uint64_t msr_mtrr_fixed[NUM_FIXED_MSR];
+ uint64_t msr_mtrr_cap;
+ uint64_t msr_mtrr_def_type;
+};
+
+DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr);
+
/*
* Largest type-code in use
*/
-#define HVM_SAVE_CODE_MAX 13
+#define HVM_SAVE_CODE_MAX 14
#endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */
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