# HG changeset patch
# User Keir Fraser <keir@xxxxxxxxxxxxx>
# Date 1192183226 -3600
# Node ID ac37f61f69081837469c196a05c11e28a6f12008
# Parent 4746c8c9372fd1b2c9db48210a9be2c3eb0bdb77
svm: allow guest to use EFER.FFXSE
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>
---
xen/arch/x86/hvm/hvm.c | 9 ++++++---
xen/arch/x86/hvm/svm/svm.c | 2 --
xen/include/asm-x86/cpufeature.h | 5 ++++-
xen/include/asm-x86/msr-index.h | 6 +++++-
4 files changed, 15 insertions(+), 7 deletions(-)
diff -r 4746c8c9372f -r ac37f61f6908 xen/arch/x86/hvm/hvm.c
--- a/xen/arch/x86/hvm/hvm.c Fri Oct 12 10:19:55 2007 +0100
+++ b/xen/arch/x86/hvm/hvm.c Fri Oct 12 11:00:26 2007 +0100
@@ -358,10 +358,12 @@ static int hvm_load_cpu_ctxt(struct doma
return -EINVAL;
}
- if ( (ctxt.msr_efer & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
+ if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LME | EFER_LMA |
+ EFER_NX | EFER_SCE)) ||
((sizeof(long) != 8) && (ctxt.msr_efer & EFER_LME)) ||
(!cpu_has_nx && (ctxt.msr_efer & EFER_NX)) ||
(!cpu_has_syscall && (ctxt.msr_efer & EFER_SCE)) ||
+ (!cpu_has_ffxsr && (ctxt.msr_efer & EFER_FFXSE)) ||
((ctxt.msr_efer & (EFER_LME|EFER_LMA)) == EFER_LMA) )
{
gdprintk(XENLOG_ERR, "HVM restore: bad EFER 0x%"PRIx64"\n",
@@ -576,10 +578,11 @@ int hvm_set_efer(uint64_t value)
value &= ~EFER_LMA;
- if ( (value & ~(EFER_LME | EFER_NX | EFER_SCE)) ||
+ if ( (value & ~(EFER_FFXSE | EFER_LME | EFER_NX | EFER_SCE)) ||
((sizeof(long) != 8) && (value & EFER_LME)) ||
(!cpu_has_nx && (value & EFER_NX)) ||
- (!cpu_has_syscall && (value & EFER_SCE)) )
+ (!cpu_has_syscall && (value & EFER_SCE)) ||
+ (!cpu_has_ffxsr && (value & EFER_FFXSE)) )
{
gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
"EFER: %"PRIx64"\n", value);
diff -r 4746c8c9372f -r ac37f61f6908 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c Fri Oct 12 10:19:55 2007 +0100
+++ b/xen/arch/x86/hvm/svm/svm.c Fri Oct 12 11:00:26 2007 +0100
@@ -1036,8 +1036,6 @@ static void svm_vmexit_do_cpuid(struct v
/* So far, we do not support 3DNow for the guest. */
clear_bit(X86_FEATURE_3DNOW & 31, &edx);
clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
- /* no FFXSR instructions feature. */
- clear_bit(X86_FEATURE_FFXSR & 31, &edx);
}
else if ( input == 0x80000007 || input == 0x8000000A )
{
diff -r 4746c8c9372f -r ac37f61f6908 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Fri Oct 12 10:19:55 2007 +0100
+++ b/xen/include/asm-x86/cpufeature.h Fri Oct 12 11:00:26 2007 +0100
@@ -49,6 +49,7 @@
#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
@@ -94,7 +95,6 @@
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
-#define X86_FEATURE_FFXSR (6*32+25) /* FFXSR instruction optimizations */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
@@ -147,6 +147,9 @@
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
#endif
+#define cpu_has_ffxsr ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
+ && boot_cpu_has(X86_FEATURE_FFXSR))
+
#endif /* __ASM_I386_CPUFEATURE_H */
/*
diff -r 4746c8c9372f -r ac37f61f6908 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Fri Oct 12 10:19:55 2007 +0100
+++ b/xen/include/asm-x86/msr-index.h Fri Oct 12 11:00:26 2007 +0100
@@ -18,13 +18,17 @@
#define _EFER_LME 8 /* Long mode enable */
#define _EFER_LMA 10 /* Long mode active (read-only) */
#define _EFER_NX 11 /* No execute enable */
-#define _EFER_SVME 12
+#define _EFER_SVME 12 /* AMD: SVM enable */
+#define _EFER_LMSLE 13 /* AMD: Long-mode segment limit enable */
+#define _EFER_FFXSE 14 /* AMD: Fast FXSAVE/FXRSTOR enable */
#define EFER_SCE (1<<_EFER_SCE)
#define EFER_LME (1<<_EFER_LME)
#define EFER_LMA (1<<_EFER_LMA)
#define EFER_NX (1<<_EFER_NX)
#define EFER_SVME (1<<_EFER_SVME)
+#define EFER_LMSLE (1<<_EFER_LMSLE)
+#define EFER_FFXSE (1<<_EFER_FFXSE)
/* Intel MSRs. Some also available on other CPUs */
#define MSR_IA32_PERFCTR0 0x000000c1
_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog
|
Home