# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1186942003 21600
# Node ID 82f5fbe59e264465397d757b70874f45dd8c2b6c
# Parent 87a72ba32301ceb894e065d760953aa98730c0cd
[IA64] Use defines instead of hard coded numbers
Some minor instruction grouping enhancements
Signed-off-by: Juergen Gross juergen.gross@xxxxxxxxxxxxxxxxxxx
---
xen/arch/ia64/xen/hyperprivop.S | 525 +++++++++++++++++++---------------------
xen/include/asm-ia64/vmmu.h | 5
xen/include/asm-ia64/xenkregs.h | 12
3 files changed, 278 insertions(+), 264 deletions(-)
diff -r 87a72ba32301 -r 82f5fbe59e26 xen/arch/ia64/xen/hyperprivop.S
--- a/xen/arch/ia64/xen/hyperprivop.S Wed Aug 08 20:48:11 2007 -0600
+++ b/xen/arch/ia64/xen/hyperprivop.S Sun Aug 12 12:06:43 2007 -0600
@@ -14,12 +14,12 @@
#include <asm/system.h>
#include <asm/debugger.h>
#include <asm/asm-xsi-offsets.h>
+#include <asm/pgtable.h>
+#include <asm/vmmu.h>
#include <public/xen.h>
-#define _PAGE_PPN_MASK 0x0003fffffffff000 //asm/pgtable.h doesn't do
assembly
-#define PAGE_PHYS (0x0010000000000661 | _PAGE_PL_PRIV)
- //__pgprot(__DIRTY_BITS|_PAGE_PL_PRIV|_PAGE_AR_RWX)
+#define PAGE_PHYS (__DIRTY_BITS | _PAGE_PL_PRIV | _PAGE_AR_RWX)
#if 1 // change to 0 to turn off all fast paths
# define FAST_HYPERPRIVOPS
@@ -221,7 +221,7 @@ ENTRY(hyper_ssm_i)
br.spnt.few dispatch_break_fault ;;
#endif
// give up for now if: ipsr.be==1, ipsr.pp==1
- mov r30=cr.ipsr;;
+ mov r30=cr.ipsr
mov r29=cr.iip;;
extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
cmp.ne p7,p0=r21,r0
@@ -236,23 +236,23 @@ ENTRY(hyper_ssm_i)
st4 [r20]=r21;;
#endif
// set shared_mem iip to instruction after HYPER_SSM_I
- extr.u r20=r30,41,2 ;;
+ extr.u r20=r30,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r20 ;;
(p6) mov r20=0
(p6) adds r29=16,r29
(p7) adds r20=1,r20 ;;
- dep r30=r20,r30,41,2;; // adjust cr.ipsr.ri but don't save yet
+ dep r30=r20,r30,IA64_PSR_RI_BIT,2 // adjust cr.ipsr.ri but don't
save yet
adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r29 ;;
// set shared_mem isr
- extr.u r16=r16,38,1;; // grab cr.isr.ir bit
- dep r16=r16,r0,38,1 ;; // insert into cr.isr (rest of bits zero)
- dep r16=r20,r16,41,2 ;; // deposit cr.isr.ri
+ extr.u r16=r16,IA64_ISR_IR_BIT,1;; // grab cr.isr.ir bit
+ dep r16=r16,r0,IA64_ISR_IR_BIT,1;; // insert into cr.isr (rest of
bits zero)
+ dep r16=r20,r16,IA64_PSR_RI_BIT,2 // deposit cr.isr.ri
adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r16 ;;
+ st8 [r21]=r16
// set cr.ipsr
- mov r29=r30 ;;
- movl r28=DELIVER_PSR_SET;;
+ mov r29=r30
+ movl r28=DELIVER_PSR_SET
movl r27=~DELIVER_PSR_CLR;;
and r29=r29,r27;;
or r29=r29,r28;;
@@ -265,9 +265,8 @@ ENTRY(hyper_ssm_i)
extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
(p7) dep r30=0,r30,IA64_PSR_CPL0_BIT,2
- ;;
// FOR SSM_I ONLY, also turn on psr.i and psr.ic
- movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC);;
+ movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT|IA64_PSR_I|IA64_PSR_IC)
// movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
movl r27=~(IA64_PSR_BE|IA64_PSR_BN);;
or r30=r30,r28;;
@@ -276,7 +275,6 @@ ENTRY(hyper_ssm_i)
movl r22=THIS_CPU(current_psr_i_addr)
adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r22=[r22]
- ;;
adds r27=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
ld1 r28=[r27];;
st1 [r27]=r0
@@ -290,7 +288,7 @@ ENTRY(hyper_ssm_i)
// cover and set shared_mem precover_ifs to cr.ifs
// set shared_mem ifs to 0
cover ;;
- mov r20=cr.ifs;;
+ mov r20=cr.ifs
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
@@ -306,28 +304,28 @@ ENTRY(hyper_ssm_i)
mov r30=r2
mov r29=r3
;;
- adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
- adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
+ adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
+ adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
// temporarily save ar.unat
mov r28=ar.unat
bsw.1;;
// FIXME?: ar.unat is not really handled correctly,
// but may not matter if the OS is NaT-clean
- .mem.offset 0,0; st8.spill [r2]=r16,16;
+ .mem.offset 0,0; st8.spill [r2]=r16,16
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r18,16;
+ .mem.offset 0,0; st8.spill [r2]=r18,16
.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r20,16;
+ .mem.offset 0,0; st8.spill [r2]=r20,16
.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r22,16;
+ .mem.offset 0,0; st8.spill [r2]=r22,16
.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r24,16;
+ .mem.offset 0,0; st8.spill [r2]=r24,16
.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r26,16;
+ .mem.offset 0,0; st8.spill [r2]=r26,16
.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r28,16;
+ .mem.offset 0,0; st8.spill [r2]=r28,16
.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r30,16;
+ .mem.offset 0,0; st8.spill [r2]=r30,16
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
bsw.0 ;;
mov r27=ar.unat
@@ -339,7 +337,7 @@ ENTRY(hyper_ssm_i)
mov r2=r30
mov r3=r29
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r20]=r0 ;;
+ st4 [r20]=r0
mov pr=r31,-1 ;;
rfi
;;
@@ -357,7 +355,7 @@ GLOBAL_ENTRY(fast_tick_reflect)
cmp.ne p6,p0=r28,r30
(p6) br.cond.spnt.few rp;;
movl r20=THIS_CPU(cpu_info)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
- ld8 r26=[r20];;
+ ld8 r26=[r20]
mov r27=ar.itc;;
adds r27=200,r27;; // safety margin
cmp.ltu p6,p0=r26,r27
@@ -371,9 +369,9 @@ GLOBAL_ENTRY(fast_tick_reflect)
cmp.ne p6,p0=r21,r0
(p6) br.cond.spnt.few rp;;
// definitely have a domain tick
- mov cr.eoi=r0;;
- mov rp=r29;;
- mov cr.itm=r26;; // ensure next tick
+ mov cr.eoi=r0
+ mov rp=r29
+ mov cr.itm=r26 // ensure next tick
#ifdef FAST_REFLECT_CNT
movl r20=PERFC(fast_reflect + (0x3000>>8));;
ld4 r21=[r20];;
@@ -392,29 +390,29 @@ GLOBAL_ENTRY(fast_tick_reflect)
tbit.nz p6,p0=r20,16;; // check itv.m (discard) bit
(p6) br.cond.spnt.few fast_tick_reflect_done;;
extr.u r27=r20,0,6 // r27 has low 6 bits of itv.vector
- extr.u r26=r20,6,2;; // r26 has irr index of itv.vector
+ extr.u r26=r20,6,2 // r26 has irr index of itv.vector
movl r19=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r19=[r19];;
adds r22=IA64_VCPU_DOMAIN_ITM_LAST_OFFSET,r19
adds r23=IA64_VCPU_DOMAIN_ITM_OFFSET,r19;;
- ld8 r24=[r22];;
+ ld8 r24=[r22]
ld8 r23=[r23];;
cmp.eq p6,p0=r23,r24 // skip if this tick already delivered
(p6) br.cond.spnt.few fast_tick_reflect_done;;
// set irr bit
- adds r21=IA64_VCPU_IRR0_OFFSET,r19;
+ adds r21=IA64_VCPU_IRR0_OFFSET,r19
shl r26=r26,3;;
- add r21=r21,r26;;
+ add r21=r21,r26
mov r25=1;;
- shl r22=r25,r27;;
+ shl r22=r25,r27
ld8 r23=[r21];;
or r22=r22,r23;;
- st8 [r21]=r22;;
+ st8 [r21]=r22
// set evtchn_upcall_pending!
adds r20=XSI_PSR_I_ADDR_OFS-XSI_PSR_IC_OFS,r18;;
ld8 r20=[r20];;
adds r20=-1,r20;; // evtchn_upcall_pending
- st1 [r20]=r25;;
+ st1 [r20]=r25
// if interrupted at pl0, we're done
extr.u r16=r17,IA64_PSR_CPL0_BIT,2;;
cmp.eq p6,p0=r16,r0;;
@@ -432,20 +430,20 @@ GLOBAL_ENTRY(fast_tick_reflect)
// r18 == XSI_PSR_IC
// r19 == IA64_KR(CURRENT)
// r31 == pr
- mov r16=cr.isr;;
- mov r29=cr.iip;;
+ mov r16=cr.isr
+ mov r29=cr.iip
adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r29 ;;
+ st8 [r21]=r29
// set shared_mem isr
- extr.u r16=r16,38,1;; // grab cr.isr.ir bit
- dep r16=r16,r0,38,1 ;; // insert into cr.isr (rest of bits zero)
- extr.u r20=r17,41,2 ;; // get ipsr.ri
- dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
- adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r16 ;;
+ extr.u r16=r16,IA64_ISR_IR_BIT,1;; // grab cr.isr.ir bit
+ dep r16=r16,r0,IA64_ISR_IR_BIT,1 // insert into cr.isr (rest of
bits zero)
+ extr.u r20=r17,IA64_PSR_RI_BIT,2;; // get ipsr.ri
+ dep r16=r20,r16,IA64_PSR_RI_BIT,2 // deposit cr.isr.ei
+ adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18;;
+ st8 [r21]=r16
// set cr.ipsr (make sure cpl==2!)
- mov r29=r17 ;;
- movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
+ mov r29=r17
+ movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
and r29=r29,r27;;
or r29=r29,r28;;
@@ -454,94 +452,93 @@ GLOBAL_ENTRY(fast_tick_reflect)
extr.u r29=r17,IA64_PSR_CPL0_BIT,2;;
cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
(p7) dep r17=0,r17,IA64_PSR_CPL0_BIT,2
- ;;
- movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
+ movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
or r17=r17,r28;;
- and r17=r17,r27;;
+ and r17=r17,r27
ld4 r16=[r18];;
- cmp.ne p6,p0=r16,r0;;
+ cmp.ne p6,p0=r16,r0
movl r22=THIS_CPU(current_psr_i_addr);;
ld8 r22=[r22]
(p6) dep r17=-1,r17,IA64_PSR_IC_BIT,1 ;;
ld1 r16=[r22];;
cmp.eq p6,p0=r16,r0;;
-(p6) dep r17=-1,r17,IA64_PSR_I_BIT,1 ;;
+(p6) dep r17=-1,r17,IA64_PSR_I_BIT,1
mov r20=1
- adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r17 ;;
+ adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18;;
+ st8 [r21]=r17
// set shared_mem interrupt_delivery_enabled to 0
// set shared_mem interrupt_collection_enabled to 0
- st1 [r22]=r20;;
+ st1 [r22]=r20
st4 [r18]=r0;;
// cover and set shared_mem precover_ifs to cr.ifs
// set shared_mem ifs to 0
cover ;;
- mov r20=cr.ifs;;
+ mov r20=cr.ifs
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r20 ;;
+ st8 [r21]=r20
// leave cr.ifs alone for later rfi
// set iip to go to domain IVA break instruction vector
adds r22=IA64_VCPU_IVA_OFFSET,r19;;
- ld8 r23=[r22];;
+ ld8 r23=[r22]
movl r24=0x3000;;
add r24=r24,r23;;
- mov cr.iip=r24;;
+ mov cr.iip=r24
// OK, now all set to go except for switch to virtual bank0
mov r30=r2
mov r29=r3
#ifdef HANDLE_AR_UNAT
- mov r28=ar.unat;
+ mov r28=ar.unat
#endif
;;
adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
;;
bsw.1;;
- .mem.offset 0,0; st8.spill [r2]=r16,16;
+ .mem.offset 0,0; st8.spill [r2]=r16,16
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r18,16;
+ .mem.offset 0,0; st8.spill [r2]=r18,16
.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r20,16;
+ .mem.offset 0,0; st8.spill [r2]=r20,16
.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r22,16;
+ .mem.offset 0,0; st8.spill [r2]=r22,16
.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r24,16;
+ .mem.offset 0,0; st8.spill [r2]=r24,16
.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r26,16;
+ .mem.offset 0,0; st8.spill [r2]=r26,16
.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r28,16;
+ .mem.offset 0,0; st8.spill [r2]=r28,16
.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r30,16;
+ .mem.offset 0,0; st8.spill [r2]=r30,16
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
#ifdef HANDLE_AR_UNAT
// r16~r23 are preserved regsin bank0 regs, we need to restore them,
// r24~r31 are scratch regs, we don't need to handle NaT bit,
// because OS handler must assign it before access it
- ld8 r16=[r2],16;
+ ld8 r16=[r2],16
ld8 r17=[r3],16;;
- ld8 r18=[r2],16;
+ ld8 r18=[r2],16
ld8 r19=[r3],16;;
- ld8 r20=[r2],16;
+ ld8 r20=[r2],16
ld8 r21=[r3],16;;
- ld8 r22=[r2],16;
+ ld8 r22=[r2],16
ld8 r23=[r3],16;;
#endif
;;
bsw.0 ;;
- mov r24=ar.unat;
+ mov r24=ar.unat
mov r2=r30
mov r3=r29
#ifdef HANDLE_AR_UNAT
- mov ar.unat=r28;
-#endif
- ;;
- adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
+ mov ar.unat=r28
+#endif
+ ;;
+ adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r25]=r24;
- st4 [r20]=r0 ;;
+ st8 [r25]=r24
+ st4 [r20]=r0
fast_tick_reflect_done:
mov pr=r31,-1 ;;
rfi
@@ -557,13 +554,13 @@ GLOBAL_ENTRY(fast_break_reflect)
#ifndef FAST_BREAK // see beginning of file
br.sptk.many dispatch_break_fault ;;
#endif
- mov r30=cr.ipsr;;
+ mov r30=cr.ipsr
mov r29=cr.iip;;
extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
- cmp.ne p7,p0=r21,r0 ;;
+ cmp.ne p7,p0=r21,r0
(p7) br.spnt.few dispatch_break_fault ;;
extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
- cmp.ne p7,p0=r21,r0 ;;
+ cmp.ne p7,p0=r21,r0
(p7) br.spnt.few dispatch_break_fault ;;
movl r20=IA64_PSR_CPL ;;
and r22=r20,r30 ;;
@@ -579,17 +576,17 @@ 1:
1:
#if 1 /* special handling in case running on simulator */
movl r20=first_break;;
- ld4 r23=[r20];;
- movl r21=0x80001;
+ ld4 r23=[r20]
+ movl r21=0x80001
movl r22=0x80002;;
- cmp.ne p7,p0=r23,r0;;
+ cmp.ne p7,p0=r23,r0
(p7) br.spnt.few dispatch_break_fault ;;
- cmp.eq p7,p0=r21,r17;
+ cmp.eq p7,p0=r21,r17
(p7) br.spnt.few dispatch_break_fault ;;
- cmp.eq p7,p0=r22,r17;
+ cmp.eq p7,p0=r22,r17
(p7) br.spnt.few dispatch_break_fault ;;
#endif
- movl r20=0x2c00;
+ movl r20=0x2c00
// save iim in shared_info
adds r21=XSI_IIM_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r17;;
@@ -606,7 +603,7 @@ END(fast_break_reflect)
// r31 == pr
ENTRY(fast_reflect)
#ifdef FAST_REFLECT_CNT
- movl r22=PERFC(fast_reflect);
+ movl r22=PERFC(fast_reflect)
shr r23=r20,8-2;;
add r22=r22,r23;;
ld4 r21=[r22];;
@@ -622,7 +619,7 @@ ENTRY(fast_reflect)
movl r21=THIS_CPU(current_psr_i_addr)
mov r29=r30 ;;
ld8 r21=[r21]
- movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
+ movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1);;
and r29=r29,r27;;
or r29=r29,r28;;
@@ -635,30 +632,28 @@ ENTRY(fast_reflect)
extr.u r29=r30,IA64_PSR_CPL0_BIT,2;;
cmp.eq p7,p0=CONFIG_CPL0_EMUL,r29;;
(p7) dep r30=0,r30,IA64_PSR_CPL0_BIT,2
- ;;
- movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
+ movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT)
movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN);;
or r30=r30,r28;;
- and r30=r30,r27;;
+ and r30=r30,r27
// also set shared_mem ipsr.i and ipsr.ic appropriately
ld1 r22=[r21]
ld4 r24=[r18];;
cmp4.eq p6,p7=r24,r0;;
(p6) dep r30=0,r30,IA64_PSR_IC_BIT,1
-(p7) dep r30=-1,r30,IA64_PSR_IC_BIT,1 ;;
+(p7) dep r30=-1,r30,IA64_PSR_IC_BIT,1
mov r24=r21
cmp.ne p6,p7=r22,r0;;
(p6) dep r30=0,r30,IA64_PSR_I_BIT,1
-(p7) dep r30=-1,r30,IA64_PSR_I_BIT,1 ;;
+(p7) dep r30=-1,r30,IA64_PSR_I_BIT,1
mov r22=1
adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
- ;;
adds r27=XSI_VPSR_DFH_OFS-XSI_PSR_IC_OFS,r18;;
ld1 r28=[r27];;
st1 [r27]=r0
dep r30=r28,r30,IA64_PSR_DFH_BIT,1
;;
- st8 [r21]=r30 ;;
+ st8 [r21]=r30
// set shared_mem interrupt_delivery_enabled to 0
// set shared_mem interrupt_collection_enabled to 0
st1 [r24]=r22
@@ -666,11 +661,11 @@ ENTRY(fast_reflect)
// cover and set shared_mem precover_ifs to cr.ifs
// set shared_mem ifs to 0
cover ;;
- mov r24=cr.ifs;;
+ mov r24=cr.ifs
adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r0 ;;
adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r21]=r24 ;;
+ st8 [r21]=r24
// FIXME: need to save iipa and isr to be arch-compliant
// set iip to go to domain IVA break instruction vector
movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
@@ -678,59 +673,60 @@ ENTRY(fast_reflect)
adds r22=IA64_VCPU_IVA_OFFSET,r22;;
ld8 r23=[r22];;
add r20=r20,r23;;
- mov cr.iip=r20;;
+ mov cr.iip=r20
// OK, now all set to go except for switch to virtual bank0
mov r30=r2
mov r29=r3
#ifdef HANDLE_AR_UNAT
- mov r28=ar.unat;
-#endif
- adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
+ mov r28=ar.unat
+#endif
+ ;;
+ adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
;;
bsw.1;;
- .mem.offset 0,0; st8.spill [r2]=r16,16;
+ .mem.offset 0,0; st8.spill [r2]=r16,16
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r18,16;
+ .mem.offset 0,0; st8.spill [r2]=r18,16
.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r20,16;
+ .mem.offset 0,0; st8.spill [r2]=r20,16
.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r22,16;
+ .mem.offset 0,0; st8.spill [r2]=r22,16
.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r24,16;
+ .mem.offset 0,0; st8.spill [r2]=r24,16
.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r26,16;
+ .mem.offset 0,0; st8.spill [r2]=r26,16
.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r28,16;
+ .mem.offset 0,0; st8.spill [r2]=r28,16
.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r30,16;
+ .mem.offset 0,0; st8.spill [r2]=r30,16
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
#ifdef HANDLE_AR_UNAT
// r16~r23 are preserved regs in bank0 regs, we need to restore them,
// r24~r31 are scratch regs, we don't need to handle NaT bit,
// because OS handler must assign it before access it
- ld8 r16=[r2],16;
+ ld8 r16=[r2],16
ld8 r17=[r3],16;;
- ld8 r18=[r2],16;
+ ld8 r18=[r2],16
ld8 r19=[r3],16;;
- ld8 r20=[r2],16;
+ ld8 r20=[r2],16
ld8 r21=[r3],16;;
- ld8 r22=[r2],16;
+ ld8 r22=[r2],16
ld8 r23=[r3],16;;
#endif
;;
bsw.0 ;;
- mov r24=ar.unat;
+ mov r24=ar.unat
mov r2=r30
mov r3=r29
#ifdef HANDLE_AR_UNAT
- mov ar.unat=r28;
-#endif
- ;;
- adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
+ mov ar.unat=r28
+#endif
+ ;;
+ adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r25]=r24;
- st4 [r20]=r0 ;;
+ st8 [r25]=r24
+ st4 [r20]=r0
mov pr=r31,-1 ;;
rfi
;;
@@ -746,7 +742,7 @@ GLOBAL_ENTRY(fast_access_reflect)
#ifndef FAST_ACCESS_REFLECT // see beginning of file
br.spnt.few dispatch_reflection ;;
#endif
- mov r30=cr.ipsr;;
+ mov r30=cr.ipsr
mov r29=cr.iip;;
extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
cmp.ne p7,p0=r21,r0
@@ -763,7 +759,7 @@ GLOBAL_ENTRY(fast_access_reflect)
cmp.eq p7,p0=r0,r21
(p7) br.spnt.few dispatch_reflection ;;
// set shared_mem ifa, FIXME: should we validate it?
- mov r17=cr.ifa;;
+ mov r17=cr.ifa
adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r17 ;;
// get rr[ifa] and save to itir in shared memory (extra bits ignored)
@@ -827,17 +823,17 @@ GLOBAL_ENTRY(fast_tlb_miss_reflect)
(p7) br.spnt.few page_fault ;;
fast_tlb_no_tr_match:
movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
- ld8 r27=[r27];;
+ ld8 r27=[r27]
tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
-(p6) adds r25=IA64_VCPU_ITLB_OFFSET,r27;;
+(p6) adds r25=IA64_VCPU_ITLB_OFFSET,r27
(p7) adds r25=IA64_VCPU_DTLB_OFFSET,r27;;
ld8 r20=[r25],8;;
- tbit.z p7,p0=r20,0;; // present?
+ tbit.z p7,p0=r20,VTLB_PTE_P_BIT // present?
(p7) br.cond.spnt.few 1f;;
// if ifa is in range of tlb, don't bother to check rid, go slow path
ld8 r21=[r25],8;;
mov r23=1
- extr.u r21=r21,2,6;;
+ extr.u r21=r21,IA64_ITIR_PS,IA64_ITIR_PS_LEN;;
shl r22=r23,r21
ld8 r21=[r25],8;;
cmp.ltu p7,p0=r17,r21
@@ -853,9 +849,9 @@ 1: // check the guest VHPT
(p7) br.cond.spnt.few page_fault;;
// if (!rr.ve || !(pta & IA64_PTA_VE)) take slow way for now
// FIXME: later, we deliver an alt_d/i vector after thash and itir
- tbit.z p7,p0=r19,IA64_PTA_VE_BIT;; //
+ tbit.z p7,p0=r19,IA64_PTA_VE_BIT
(p7) br.cond.spnt.few page_fault;;
- extr.u r25=r17,61,3;;
+ extr.u r25=r17,61,3
adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
shl r25=r25,3;;
add r21=r21,r25;;
@@ -864,7 +860,7 @@ 1: // check the guest VHPT
(p7) br.cond.spnt.few page_fault;;
// compute and save away itir (r22 & RR_PS_MASK)
- movl r21=0xfc;;
+ movl r21=IA64_ITIR_PS_MASK;;
and r22=r22,r21;;
adds r21=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r21]=r22;;
@@ -887,17 +883,16 @@ 1: // check the guest VHPT
ld8 r24 = [r19] // pta
;;
ld8 r23 = [r27] // rrs[vadr>>61]
- extr.u r26 = r24, 2, 6
- ;;
- extr.u r22 = r23, 2, 6
- shl r30 = r25, r26
- ;;
- shr.u r19 = r17, r22
- shr.u r29 = r24, 15
- ;;
- adds r30 = -1, r30
- ;;
- shladd r27 = r19, 3, r0
+ extr.u r26 = r24, IA64_PTA_SIZE_BIT, IA64_PTA_SIZE_LEN
+ ;;
+ extr.u r22 = r23, IA64_RR_PS, IA64_RR_PS_LEN
+ shl r30 = r25, r26 // pt size
+ ;;
+ shr.u r19 = r17, r22 // ifa pg number
+ shr.u r29 = r24, IA64_PTA_BASE_BIT
+ adds r30 = -1, r30 // pt size mask
+ ;;
+ shladd r27 = r19, 3, r0 // vhpt offset
extr.u r26 = r30, 15, 46
;;
andcm r24 = r29, r26
@@ -916,7 +911,7 @@ 1: // check the guest VHPT
or r19 = r19, r30
;;
adds r23=XSI_IHA_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r23]=r19;;
+ st8 [r23]=r19
// done with thash, check guest VHPT
adds r20 = XSI_PTA_OFS-XSI_PSR_IC_OFS, r18;;
@@ -925,7 +920,7 @@ 1: // check the guest VHPT
// if (((r17=address ^ r24=pta) & ((itir_mask(pta) << 3) >> 3)) != 0) {
mov r20=-8
xor r21=r17,r24
- extr.u r24=r24,2,6;;
+ extr.u r24=r24,IA64_PTA_SIZE_BIT,IA64_PTA_SIZE_LEN;;
shl r20=r20,r24;;
shr.u r20=r20,3;;
and r21=r20,r21;;
@@ -934,7 +929,7 @@ 1: // check the guest VHPT
// __copy_from_user(&pte, r19=(void *)(*iha), sizeof(pte)=8)
// prepare for possible nested dtlb fault
mov r29=b0
- movl r30=guest_vhpt_miss;;
+ movl r30=guest_vhpt_miss
// now go fetch the entry from the guest VHPT
ld8 r20=[r19];;
// if we wind up here, we successfully loaded the VHPT entry
@@ -961,14 +956,14 @@ 1: // check the guest VHPT
// r30 == recovery ip if failure occurs
// r31 == pr
tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
-(p6) mov r17=1;;
-(p7) mov r17=0;;
+(p6) mov r17=1
+(p7) mov r17=0
mov r16=r20
- mov r29=b0 ;;
- movl r30=recover_and_page_fault ;;
+ mov r29=b0
+ movl r30=recover_and_page_fault
adds r21=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r24=[r21];;
- extr.u r24=r24,2,6;;
+ extr.u r24=r24,IA64_ITIR_PS,IA64_ITIR_PS_LEN
// IFA already in PSCB
br.cond.sptk.many fast_insert;;
END(fast_tlb_miss_reflect)
@@ -981,13 +976,13 @@ ENTRY(recover_and_page_fault)
adds r22=1,r22;;
st4 [r21]=r22;;
#endif
- mov b0=r29;;
+ mov b0=r29
br.cond.sptk.many page_fault;;
// if we wind up here, we missed in guest VHPT so recover
// from nested dtlb fault and reflect a tlb fault to the guest
guest_vhpt_miss:
- mov b0=r29;;
+ mov b0=r29
// fault = IA64_VHPT_FAULT
mov r20=r0
br.cond.sptk.many 1f;
@@ -998,18 +993,18 @@ guest_vhpt_miss:
// see vcpu_get_itir_on_fault: get ps,rid,(FIXME key) from rr[ifa]
page_not_present:
tbit.nz p6,p7=r16,IA64_ISR_X_BIT;;
-(p6) movl r20=0x400;;
-(p7) movl r20=0x800;;
+(p6) movl r20=0x400
+(p7) movl r20=0x800
1: extr.u r25=r17,61,3;;
- adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
+ adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
shl r25=r25,3;;
add r21=r21,r25;;
ld8 r22=[r21];;
- extr.u r22=r22,2,30;;
- dep.z r22=r22,2,30;;
+ extr.u r22=r22,IA64_RR_PS,IA64_RR_PS_LEN+IA64_RR_RID_LEN;;
+ dep.z r22=r22,IA64_RR_PS,IA64_RR_PS_LEN+IA64_RR_RID_LEN
adds r23=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
- st8 [r23]=r22;;
+ st8 [r23]=r22
// fast reflect expects
// r16 == cr.isr
@@ -1160,36 +1155,39 @@ just_do_rfi:
cmp.ne p7,p0=r21,r0 // domain already did "bank 1 switch?"
(p7) br.cond.spnt.few 1f;
// OK, now all set to go except for switch to virtual bank1
- mov r22=1;; st4 [r20]=r22;
- mov r30=r2; mov r29=r3;;
- mov r17=ar.unat;;
- adds r16=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
- adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
+ mov r22=1;;
+ st4 [r20]=r22
+ mov r30=r2
+ mov r29=r3
+ mov r17=ar.unat;;
+ adds r16=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18
+ adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
- ld8 r16=[r16];;
- mov ar.unat=r16;;
+ ld8 r16=[r16];;
+ mov ar.unat=r16;;
bsw.1;;
// FIXME?: ar.unat is not really handled correctly,
// but may not matter if the OS is NaT-clean
- .mem.offset 0,0; ld8.fill r16=[r2],16 ;
+ .mem.offset 0,0; ld8.fill r16=[r2],16
.mem.offset 8,0; ld8.fill r17=[r3],16 ;;
- .mem.offset 0,0; ld8.fill r18=[r2],16 ;
+ .mem.offset 0,0; ld8.fill r18=[r2],16
.mem.offset 0,0; ld8.fill r19=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r20=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r20=[r2],16
.mem.offset 8,0; ld8.fill r21=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r22=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r22=[r2],16
.mem.offset 8,0; ld8.fill r23=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r24=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r24=[r2],16
.mem.offset 8,0; ld8.fill r25=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r26=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r26=[r2],16
.mem.offset 8,0; ld8.fill r27=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r28=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r28=[r2],16
.mem.offset 8,0; ld8.fill r29=[r3],16 ;;
- .mem.offset 8,0; ld8.fill r30=[r2],16 ;
+ .mem.offset 8,0; ld8.fill r30=[r2],16
.mem.offset 8,0; ld8.fill r31=[r3],16 ;;
bsw.0 ;;
- mov ar.unat=r17;;
- mov r2=r30; mov r3=r29;;
+ mov ar.unat=r17
+ mov r2=r30
+ mov r3=r29
1: mov pr=r31,-1
;;
rfi
@@ -1204,7 +1202,7 @@ ENTRY(rfi_check_extint)
// make sure none of these get trashed in case going to just_do_rfi
movl r30=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r30=[r30];;
- adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
+ adds r24=IA64_VCPU_INSVC3_OFFSET,r30
mov r25=192
adds r16=IA64_VCPU_IRR3_OFFSET,r30;;
ld8 r23=[r16];;
@@ -1223,7 +1221,6 @@ ENTRY(rfi_check_extint)
(p6) adds r24=-8,r24;;
(p6) adds r25=-64,r25;;
(p6) ld8 r23=[r16];;
-(p6) cmp.eq p6,p0=r23,r0;;
cmp.eq p6,p0=r23,r0
(p6) br.cond.spnt.few just_do_rfi; // this is actually an error
// r16 points to non-zero element of irr, r23 has value
@@ -1279,25 +1276,25 @@ ENTRY(rfi_with_interrupt)
// r21 == vipsr (ipsr in shared_mem)
// r30 == IA64_KR(CURRENT)
// r31 == pr
- mov r17=cr.ipsr;;
+ mov r17=cr.ipsr
mov r16=cr.isr;;
// set shared_mem isr
- extr.u r16=r16,38,1;; // grab cr.isr.ir bit
- dep r16=r16,r0,38,1 ;; // insert into cr.isr (rest of bits zero)
- extr.u r20=r21,41,2 ;; // get v(!)psr.ri
- dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
+ extr.u r16=r16,IA64_ISR_IR_BIT,1;; // grab cr.isr.ir bit
+ dep r16=r16,r0,IA64_ISR_IR_BIT,1 // insert into cr.isr (rest of
bits zero)
+ extr.u r20=r21,IA64_PSR_RI_BIT,2 ;; // get v(!)psr.ri
+ dep r16=r20,r16,IA64_PSR_RI_BIT,2 ;; // deposit cr.isr.ei
adds r22=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r22]=r16;;
movl r22=THIS_CPU(current_psr_i_addr)
// set cr.ipsr (make sure cpl==2!)
mov r29=r17
movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0|IA64_PSR_CPL1)
- movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT);;
+ movl r28=DELIVER_PSR_SET | (CONFIG_CPL0_EMUL << IA64_PSR_CPL0_BIT)
mov r20=1;;
ld8 r22=[r22]
and r29=r29,r27;;
or r29=r29,r28;;
- mov cr.ipsr=r29;;
+ mov cr.ipsr=r29
// v.ipsr and v.iip are already set (and v.iip validated) as rfi target
// set shared_mem interrupt_delivery_enabled to 0
// set shared_mem interrupt_collection_enabled to 0
@@ -1307,7 +1304,7 @@ ENTRY(rfi_with_interrupt)
// set shared_mem ifs to 0
#if 0
cover ;;
- mov r20=cr.ifs;;
+ mov r20=cr.ifs
adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
st8 [r22]=r0 ;;
adds r22=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
@@ -1322,38 +1319,40 @@ ENTRY(rfi_with_interrupt)
#endif
// set iip to go to domain IVA break instruction vector
adds r22=IA64_VCPU_IVA_OFFSET,r30;;
- ld8 r23=[r22];;
+ ld8 r23=[r22]
movl r24=0x3000;;
add r24=r24,r23;;
mov cr.iip=r24;;
#if 0
// OK, now all set to go except for switch to virtual bank0
- mov r30=r2; mov r29=r3;;
- adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
+ mov r30=r2
+ mov r29=r3;;
+ adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18
adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
bsw.1;;
// FIXME: need to handle ar.unat!
- .mem.offset 0,0; st8.spill [r2]=r16,16;
+ .mem.offset 0,0; st8.spill [r2]=r16,16
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r18,16;
+ .mem.offset 0,0; st8.spill [r2]=r18,16
.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r20,16;
+ .mem.offset 0,0; st8.spill [r2]=r20,16
.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r22,16;
+ .mem.offset 0,0; st8.spill [r2]=r22,16
.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r24,16;
+ .mem.offset 0,0; st8.spill [r2]=r24,16
.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r26,16;
+ .mem.offset 0,0; st8.spill [r2]=r26,16
.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r28,16;
+ .mem.offset 0,0; st8.spill [r2]=r28,16
.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
- .mem.offset 0,0; st8.spill [r2]=r30,16;
+ .mem.offset 0,0; st8.spill [r2]=r30,16
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
bsw.0 ;;
- mov r2=r30; mov r3=r29;;
+ mov r2=r30
+ mov r3=r29;;
#endif
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
- st4 [r20]=r0 ;;
+ st4 [r20]=r0
mov pr=r31,-1 ;;
rfi
END(rfi_with_interrupt)
@@ -1372,8 +1371,8 @@ ENTRY(hyper_cover)
cover ;;
mov r30=cr.ifs
adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18;;
- st8 [r22]=r30;;
- mov cr.ifs=r0;;
+ st8 [r22]=r30
+ mov cr.ifs=r0
// adjust return address to skip over break instruction
extr.u r26=r24,41,2 ;;
cmp.eq p6,p7=2,r26 ;;
@@ -1381,7 +1380,7 @@ ENTRY(hyper_cover)
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1399,7 +1398,7 @@ ENTRY(hyper_ssm_dt)
st4 [r20]=r21;;
#endif
mov r24=cr.ipsr
- mov r25=cr.iip;;
+ mov r25=cr.iip
adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
ld4 r21=[r20];;
cmp.eq p7,p0=r21,r0 // meta==0?
@@ -1410,15 +1409,15 @@ ENTRY(hyper_ssm_dt)
ld8 r23=[r22];;
mov rr[r0]=r23;;
srlz.i;;
- st4 [r20]=r0 ;;
+ st4 [r20]=r0
// adjust return address to skip over break instruction
-1: extr.u r26=r24,41,2 ;;
+1: extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1436,7 +1435,7 @@ ENTRY(hyper_rsm_dt)
st4 [r20]=r21;;
#endif
mov r24=cr.ipsr
- mov r25=cr.iip;;
+ mov r25=cr.iip
adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
ld4 r21=[r20];;
cmp.ne p7,p0=r21,r0 // meta==0?
@@ -1448,15 +1447,15 @@ ENTRY(hyper_rsm_dt)
mov rr[r0]=r23;;
srlz.i;;
adds r21=1,r0 ;;
- st4 [r20]=r21 ;;
+ st4 [r20]=r21
// adjust return address to skip over break instruction
-1: extr.u r26=r24,41,2 ;;
+1: extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1480,9 +1479,9 @@ ENTRY(hyper_set_itm)
movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r20=[r20];;
adds r20=IA64_VCPU_DOMAIN_ITM_OFFSET,r20;;
- st8 [r20]=r8;;
+ st8 [r20]=r8
cmp.geu p6,p0=r21,r8;;
-(p6) mov r21=r8;;
+(p6) mov r21=r8
// now "safe set" cr.itm=r21
mov r23=100;;
2: mov cr.itm=r21;;
@@ -1490,17 +1489,17 @@ 2: mov cr.itm=r21;;
mov r22=ar.itc ;;
cmp.leu p6,p0=r21,r22;;
add r21=r21,r23;;
- shl r23=r23,1;;
+ shl r23=r23,1
(p6) br.cond.spnt.few 2b;;
1: mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1517,7 +1516,7 @@ ENTRY(hyper_get_psr)
st4 [r20]=r21;;
#endif
mov r24=cr.ipsr
- movl r8=0x18ffffffff;;
+ movl r8=0xffffffff | IA64_PSR_MC | IA64_PSR_IT;;
// only return PSR{36:35,31:0}
and r8=r8,r24
// set vpsr.ic
@@ -1547,13 +1546,13 @@ ENTRY(hyper_get_psr)
dep r8=r21,r8,IA64_PSR_DFH_BIT,1
;;
mov r25=cr.iip
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1571,19 +1570,19 @@ ENTRY(hyper_get_rr)
st4 [r20]=r21;;
#endif
extr.u r25=r8,61,3;;
- adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
+ adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
shl r25=r25,3;;
add r20=r20,r25;;
- ld8 r8=[r20];;
+ ld8 r8=[r20]
1: mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1602,7 +1601,7 @@ ENTRY(hyper_set_rr)
adds r21=1,r21;;
st4 [r20]=r21;;
#endif
- extr.u r26=r9,8,24 // r26 = r9.rid
+ extr.u r26=r9,IA64_RR_RID,IA64_RR_RID_LEN // r26 = r9.rid
movl r20=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r20=[r20];;
adds r21=IA64_VCPU_STARTING_RID_OFFSET,r20;;
@@ -1614,7 +1613,7 @@ ENTRY(hyper_set_rr)
cmp.geu p6,p0=r22,r23 // if r9.rid + starting_rid >= ending_rid
(p6) br.cond.spnt.few 1f; // this is an error, but just ignore/return
// r21=starting_rid
- adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
+ adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
shl r25=r25,3;;
add r20=r20,r25;;
st8 [r20]=r9;; // store away exactly what was passed
@@ -1624,7 +1623,7 @@ ENTRY(hyper_set_rr)
extr.u r27=r22,0,8
extr.u r28=r22,8,8
extr.u r29=r22,16,8;;
- dep.z r23=PAGE_SHIFT,2,6;;
+ dep.z r23=PAGE_SHIFT,IA64_RR_PS,IA64_RR_PS_LEN;;
dep r23=-1,r23,0,1;; // mangling is swapping bytes 1 & 3
dep r23=r27,r23,24,8;;
dep r23=r28,r23,16,8;;
@@ -1635,13 +1634,13 @@ ENTRY(hyper_set_rr)
// done, mosey on back
1: mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1677,13 +1676,13 @@ ENTRY(hyper_set_rr0_to_rr4)
adds r25=IA64_VCPU_ENDING_RID_OFFSET,r17
;;
ld4 r22=[r21] // r22 = current->starting_rid
- extr.u r26=r8,8,24 // r26 = r8.rid
- extr.u r27=r9,8,24 // r27 = r9.rid
+ extr.u r26=r8,IA64_RR_RID,IA64_RR_RID_LEN // r26 = r8.rid
+ extr.u r27=r9,IA64_RR_RID,IA64_RR_RID_LEN // r27 = r9.rid
ld4 r23=[r25] // r23 = current->ending_rid
- extr.u r28=r10,8,24 // r28 = r10.rid
- extr.u r29=r11,8,24 // r29 = r11.rid
+ extr.u r28=r10,IA64_RR_RID,IA64_RR_RID_LEN // r28 = r10.rid
+ extr.u r29=r11,IA64_RR_RID,IA64_RR_RID_LEN // r29 = r11.rid
adds r24=IA64_VCPU_META_SAVED_RR0_OFFSET,r17
- extr.u r30=r14,8,24 // r30 = r14.rid
+ extr.u r30=r14,IA64_RR_RID,IA64_RR_RID_LEN // r30 = r14.rid
;;
add r16=r26,r22
add r17=r27,r22
@@ -1873,13 +1872,13 @@ ENTRY(hyper_set_rr0_to_rr4)
// done, mosey on back
1: mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1898,7 +1897,7 @@ ENTRY(hyper_set_kr)
adds r21=1,r21;;
st4 [r20]=r21;;
#endif
- adds r21=XSI_KR0_OFS-XSI_PSR_IC_OFS,r18 ;;
+ adds r21=XSI_KR0_OFS-XSI_PSR_IC_OFS,r18
shl r20=r8,3;;
add r22=r20,r21;;
st8 [r22]=r9;;
@@ -1929,13 +1928,13 @@ ENTRY(hyper_set_kr)
// done, mosey on back
1: mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -1970,9 +1969,9 @@ ENTRY(hyper_thash)
ld8 r24 = [r19] // pta
;;
ld8 r23 = [r27] // rrs[vadr>>61]
- extr.u r26 = r24, 2, 6
- ;;
- extr.u r22 = r23, 2, 6
+ extr.u r26 = r24, IA64_PTA_SIZE_BIT, IA64_PTA_SIZE_LEN
+ ;;
+ extr.u r22 = r23, IA64_RR_PS, IA64_RR_PS_LEN
shl r30 = r25, r26
;;
shr.u r19 = r8, r22
@@ -1999,13 +1998,13 @@ ENTRY(hyper_thash)
// done, update iip/ipsr to next instruction
mov r24=cr.ipsr
mov r25=cr.iip;;
- extr.u r26=r24,41,2 ;;
+ extr.u r26=r24,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r25=16,r25
(p7) adds r26=1,r26
;;
- dep r24=r26,r24,41,2
+ dep r24=r26,r24,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r24
mov cr.iip=r25
@@ -2072,13 +2071,13 @@ 2:
st8 [r25]=r24 // set 1-entry i/dtlb as not present
st8 [r26]=r27 ;;
// increment to point to next instruction
- extr.u r26=r29,41,2 ;;
+ extr.u r26=r29,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r30=16,r30
(p7) adds r26=1,r26
;;
- dep r29=r26,r29,41,2
+ dep r29=r26,r29,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r29
mov cr.iip=r30
@@ -2113,7 +2112,7 @@ hyper_itc_d:
// ensure itir.ps >= xen's pagesize
adds r23=XSI_ITIR_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r23=[r23];;
- extr.u r24=r23,2,6;; // r24==logps
+ extr.u r24=r23,IA64_ITIR_PS,IA64_ITIR_PS_LEN;; // r24==logps
cmp.gt p7,p0=PAGE_SHIFT,r24
(p7) br.spnt.many dispatch_break_fault ;;
adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
@@ -2125,7 +2124,7 @@ hyper_itc_d:
movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r27=[r27];;
adds r27=IA64_VCPU_DOMAIN_OFFSET,r27;;
- ld8 r27=[r27];;
+ ld8 r27=[r27]
// FIXME: is the global var dom0 always pinned? assume so for now
movl r28=dom0;;
ld8 r28=[r28];;
@@ -2134,7 +2133,7 @@ hyper_itc_d:
(p7) br.spnt.many dispatch_break_fault ;;
#ifdef FAST_HYPERPRIVOP_CNT
cmp.eq p6,p7=HYPERPRIVOP_ITC_D,r17;;
-(p6) movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_D);;
+(p6) movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_D)
(p7) movl r20=FAST_HYPERPRIVOP_PERFC(HYPERPRIVOP_ITC_I);;
ld4 r21=[r20];;
adds r21=1,r21;;
@@ -2163,10 +2162,10 @@ ENTRY(fast_insert)
// translate_domain_pte(r16=pteval,PSCB(ifa)=address,r24=itir)
mov r19=1;;
shl r20=r19,r24;;
- adds r20=-1,r20;; // r20 == mask
+ adds r20=-1,r20 // r20 == mask
movl r19=_PAGE_PPN_MASK;;
and r22=r16,r19;; // r22 == pteval & _PAGE_PPN_MASK
- andcm r19=r22,r20;;
+ andcm r19=r22,r20
adds r21=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r21=[r21];;
and r20=r21,r20;;
@@ -2178,7 +2177,7 @@ ENTRY(fast_insert)
// r16=pteval,r20=pteval2
movl r19=_PAGE_PPN_MASK
movl r21=_PAGE_PL_PRIV;;
- andcm r25=r16,r19;; // r25==pteval & ~_PAGE_PPN_MASK
+ andcm r25=r16,r19 // r25==pteval & ~_PAGE_PPN_MASK
and r22=r20,r19;;
or r22=r22,r21;;
or r22=r22,r25;; // r22==return value from translate_domain_pte
@@ -2188,12 +2187,12 @@ ENTRY(fast_insert)
// psr.ic already cleared
// NOTE: r24 still contains ps (from above)
shladd r24=r24,2,r0;;
- mov cr.itir=r24;;
+ mov cr.itir=r24
adds r23=XSI_IFA_OFS-XSI_PSR_IC_OFS,r18 ;;
ld8 r23=[r23];;
- mov cr.ifa=r23;;
+ mov cr.ifa=r23
tbit.z p6,p7=r17,0;;
-(p6) itc.d r22;;
+(p6) itc.d r22
(p7) itc.i r22;;
dv_serialize_data
// vhpt_insert(r23=vaddr,r22=pte,r24=logps<<2)
@@ -2208,30 +2207,30 @@ ENTRY(fast_insert)
st8 [r20]=r21;;
// vcpu_set_tr_entry(trp,r22=pte|1,r24=itir,r23=ifa)
// TR_ENTRY = {page_flags,itir,addr,rid}
- tbit.z p6,p7=r17,0;;
+ tbit.z p6,p7=r17,0
movl r27=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
ld8 r27=[r27];;
adds r28=IA64_VCPU_STARTING_RID_OFFSET,r27
(p6) adds r27=IA64_VCPU_DTLB_OFFSET,r27
(p7) adds r27=IA64_VCPU_ITLB_OFFSET,r27;;
st8 [r27]=r22,8;; // page_flags: already has pl >= 2 and p==1
- st8 [r27]=r24,8;; // itir
+ st8 [r27]=r24,8 // itir
mov r19=-4096;;
and r23=r23,r19;;
- st8 [r27]=r23,8;; // ifa & ~0xfff
+ st8 [r27]=r23,8 // ifa & ~0xfff
adds r29 = XSI_RR0_OFS-XSI_PSR_IC_OFS,r18
extr.u r25=r23,61,3;;
shladd r29=r25,3,r29;;
- ld8 r29=[r29];;
- movl r20=0xffffff00;;
+ ld8 r29=[r29]
+ movl r20=IA64_RR_RID_MASK;;
and r29=r29,r20;;
st8 [r27]=r29,-8;; // rid
//if ps > 12
- cmp.eq p7,p0=12<<2,r24
+ cmp.eq p7,p0=12<<IA64_ITIR_PS,r24
(p7) br.cond.sptk.many 1f;;
// if (ps > 12) {
// trp->ppn &= ~((1UL<<(ps-12))-1); trp->vadr &= ~((1UL<<ps)-1); }
- extr.u r29=r24,2,6
+ extr.u r29=r24,IA64_ITIR_PS,IA64_ITIR_PS_LEN
mov r28=1;;
shl r26=r28,r29;;
adds r29=-12,r29;;
@@ -2268,13 +2267,13 @@ 1: // done with vcpu_set_tr_entry
mov r29=cr.ipsr
mov r30=cr.iip;;
- extr.u r26=r29,41,2 ;;
+ extr.u r26=r29,IA64_PSR_RI_BIT,2 ;;
cmp.eq p6,p7=2,r26 ;;
(p6) mov r26=0
(p6) adds r30=16,r30
(p7) adds r26=1,r26
;;
- dep r29=r26,r29,41,2
+ dep r29=r26,r29,IA64_PSR_RI_BIT,2
;;
mov cr.ipsr=r29
mov cr.iip=r30;;
diff -r 87a72ba32301 -r 82f5fbe59e26 xen/include/asm-ia64/vmmu.h
--- a/xen/include/asm-ia64/vmmu.h Wed Aug 08 20:48:11 2007 -0600
+++ b/xen/include/asm-ia64/vmmu.h Sun Aug 12 12:06:43 2007 -0600
@@ -33,6 +33,7 @@
#define VTLB(v,_x) (v->arch.vtlb._x)
#define VHPT(v,_x) (v->arch.vhpt._x)
#define _PAGE_PL_PRIV (CONFIG_CPL0_EMUL << 7)
+
#ifndef __ASSEMBLY__
#include <xen/config.h>
@@ -75,10 +76,14 @@ enum {
ISIDE_TLB=0,
DSIDE_TLB=1
};
+#endif /* __ASSEMBLY__ */
+
#define VTLB_PTE_P_BIT 0
#define VTLB_PTE_IO_BIT 60
#define VTLB_PTE_IO (1UL<<VTLB_PTE_IO_BIT)
#define VTLB_PTE_P (1UL<<VTLB_PTE_P_BIT)
+
+#ifndef __ASSEMBLY__
typedef struct thash_data {
union {
struct {
diff -r 87a72ba32301 -r 82f5fbe59e26 xen/include/asm-ia64/xenkregs.h
--- a/xen/include/asm-ia64/xenkregs.h Wed Aug 08 20:48:11 2007 -0600
+++ b/xen/include/asm-ia64/xenkregs.h Sun Aug 12 12:06:43 2007 -0600
@@ -27,11 +27,13 @@
/* Page Table Address */
#define IA64_PTA_VE_BIT 0
#define IA64_PTA_SIZE_BIT 2
+#define IA64_PTA_SIZE_LEN 6
#define IA64_PTA_VF_BIT 8
#define IA64_PTA_BASE_BIT 15
#define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
-#define IA64_PTA_SIZE (__IA64_UL(0x3f) << IA64_PTA_SIZE_BIT)
+#define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
+ IA64_PTA_SIZE_BIT)
#define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
#define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
@@ -46,6 +48,14 @@
<< IA64_ITIR_KEY)
#define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
(((_key) << IA64_ITIR_KEY)))
+
+/* Region Register Bits */
+#define IA64_RR_PS 2
+#define IA64_RR_PS_LEN 6
+#define IA64_RR_RID 8
+#define IA64_RR_RID_LEN 24
+#define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
+ IA64_RR_RID
/* Define Protection Key Register (PKR) */
#define IA64_PKR_V 0
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