# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID 2a9c0f4682edfe7819e09515aedbc56b682732c0
# Parent aed7ef54fbfe31c257b54c7e6d17f480f27e2630
[IA64] Correctly not handle VHPT long format.
Signed-off-by: Tristan Gingold <tristan.gingold@xxxxxxxx>
---
xen/arch/ia64/vmx/vmx_process.c | 125 ++++++++++++++++++++++++----------------
xen/arch/ia64/vmx/vtlb.c | 8 --
2 files changed, 76 insertions(+), 57 deletions(-)
diff -r aed7ef54fbfe -r 2a9c0f4682ed xen/arch/ia64/vmx/vmx_process.c
--- a/xen/arch/ia64/vmx/vmx_process.c Wed Oct 18 22:06:49 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_process.c Wed Oct 18 22:07:06 2006 -0600
@@ -269,10 +269,12 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
int type;
u64 vhpt_adr, gppa, pteval, rr, itir;
ISR misr;
+ PTA vpta;
thash_data_t *data;
VCPU *v = current;
+
vpsr.val = VCPU(v, vpsr);
- misr.val=VMX(v,cr_isr);
+ misr.val = VMX(v,cr_isr);
if (vec == 1)
type = ISIDE_TLB;
@@ -283,7 +285,8 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
if(is_physical_mode(v)&&(!(vadr<<1>>62))){
if(vec==2){
-
if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
+ if (v->domain != dom0
+ && __gpfn_is_io(v->domain, (vadr << 1) >> (PAGE_SHIFT + 1))) {
emulate_io_inst(v,((vadr<<1)>>1),4); // UC
return IA64_FAULT;
}
@@ -322,41 +325,55 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
nested_dtlb(v);
return IA64_FAULT;
}
- } else{
- vmx_vcpu_thash(v, vadr, &vhpt_adr);
- if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
- if (!(pteval & _PAGE_P)) {
- if (vpsr.ic) {
- vcpu_set_isr(v, misr.val);
- data_page_not_present(v, vadr);
- return IA64_FAULT;
- } else {
- nested_dtlb(v);
- return IA64_FAULT;
- }
- }
- else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) {
- vcpu_get_rr(v, vadr, &rr);
- itir = rr&(RR_RID_MASK | RR_PS_MASK);
- thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
- return IA64_NO_FAULT;
- } else if (vpsr.ic) {
+ }
+
+ vmx_vcpu_get_pta(v, &vpta.val);
+ if (vpta.vf) {
+ /* Long format is not yet supported. */
+ if (vpsr.ic) {
+ vcpu_set_isr(v, misr.val);
+ dtlb_fault(v, vadr);
+ return IA64_FAULT;
+ } else {
+ nested_dtlb(v);
+ return IA64_FAULT;
+ }
+ }
+
+ vmx_vcpu_thash(v, vadr, &vhpt_adr);
+ if (!guest_vhpt_lookup(vhpt_adr, &pteval)) {
+ /* VHPT successfully read. */
+ if (!(pteval & _PAGE_P)) {
+ if (vpsr.ic) {
vcpu_set_isr(v, misr.val);
- dtlb_fault(v, vadr);
+ data_page_not_present(v, vadr);
return IA64_FAULT;
- }else{
+ } else {
nested_dtlb(v);
return IA64_FAULT;
}
+ } else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) {
+ vcpu_get_rr(v, vadr, &rr);
+ itir = rr & (RR_RID_MASK | RR_PS_MASK);
+ thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
+ return IA64_NO_FAULT;
+ } else if (vpsr.ic) {
+ vcpu_set_isr(v, misr.val);
+ dtlb_fault(v, vadr);
+ return IA64_FAULT;
}else{
- if(vpsr.ic){
- vcpu_set_isr(v, misr.val);
- dvhpt_fault(v, vadr);
- return IA64_FAULT;
- }else{
- nested_dtlb(v);
- return IA64_FAULT;
- }
+ nested_dtlb(v);
+ return IA64_FAULT;
+ }
+ } else {
+ /* Can't read VHPT. */
+ if (vpsr.ic) {
+ vcpu_set_isr(v, misr.val);
+ dvhpt_fault(v, vadr);
+ return IA64_FAULT;
+ } else {
+ nested_dtlb(v);
+ return IA64_FAULT;
}
}
}else if(type == ISIDE_TLB){
@@ -367,24 +384,34 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
vcpu_set_isr(v, misr.val);
alt_itlb(v, vadr);
return IA64_FAULT;
- } else{
- vmx_vcpu_thash(v, vadr, &vhpt_adr);
- if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
- if (pteval & _PAGE_P){
- vcpu_get_rr(v, vadr, &rr);
- itir = rr&(RR_RID_MASK | RR_PS_MASK);
- thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
- return IA64_NO_FAULT;
- } else {
- vcpu_set_isr(v, misr.val);
- inst_page_not_present(v, vadr);
- return IA64_FAULT;
- }
- }else{
- vcpu_set_isr(v, misr.val);
- ivhpt_fault(v, vadr);
- return IA64_FAULT;
- }
+ }
+
+ vmx_vcpu_get_pta(v, &vpta.val);
+ if (vpta.vf) {
+ /* Long format is not yet supported. */
+ vcpu_set_isr(v, misr.val);
+ itlb_fault(v, vadr);
+ return IA64_FAULT;
+ }
+
+
+ vmx_vcpu_thash(v, vadr, &vhpt_adr);
+ if (!guest_vhpt_lookup(vhpt_adr, &pteval)) {
+ /* VHPT successfully read. */
+ if (pteval & _PAGE_P) {
+ vcpu_get_rr(v, vadr, &rr);
+ itir = rr & (RR_RID_MASK | RR_PS_MASK);
+ thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
+ return IA64_NO_FAULT;
+ } else {
+ vcpu_set_isr(v, misr.val);
+ inst_page_not_present(v, vadr);
+ return IA64_FAULT;
+ }
+ } else {
+ vcpu_set_isr(v, misr.val);
+ ivhpt_fault(v, vadr);
+ return IA64_FAULT;
}
}
return IA64_NO_FAULT;
diff -r aed7ef54fbfe -r 2a9c0f4682ed xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c Wed Oct 18 22:06:49 2006 -0600
+++ b/xen/arch/ia64/vmx/vtlb.c Wed Oct 18 22:07:06 2006 -0600
@@ -218,20 +218,12 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
{
u64 ret;
thash_data_t * data;
- PTA vpta;
data = vhpt_lookup(iha);
if (data == NULL) {
data = vtlb_lookup(current, iha, DSIDE_TLB);
if (data != NULL)
thash_vhpt_insert(current, data->page_flags, data->itir ,iha);
- }
-
- /* VHPT long format is not read. */
- vmx_vcpu_get_pta(current, &vpta.val);
- if (vpta.vf == 1) {
- *pte = 0;
- return 0;
}
asm volatile ("rsm psr.ic|psr.i;;"
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