# HG changeset patch
# User Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
# Node ID ccdaa3ea71a7670b9d4e801d335037e0062e449f
# Parent 94aa7e921ccd079035d62841ffca76aa804b0992
[POWERPC][XEN] move setting of MSR[RI] till after SRR0/1
This also frees up space so we can properly/safely blow away larx/stcx
reservations.
Signed-off-by: Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
Signed-off-by: Hollis Blanchard <hollisb@xxxxxxxxxx>
---
xen/arch/powerpc/powerpc64/exceptions.S | 22 ++++++++++++++++------
1 files changed, 16 insertions(+), 6 deletions(-)
diff -r 94aa7e921ccd -r ccdaa3ea71a7 xen/arch/powerpc/powerpc64/exceptions.S
--- a/xen/arch/powerpc/powerpc64/exceptions.S Fri Sep 01 13:14:53 2006 -0400
+++ b/xen/arch/powerpc/powerpc64/exceptions.S Tue Sep 05 15:25:06 2006 -0400
@@ -116,12 +116,8 @@ 1:
std r0, UREGS_r13(r1) /* save R13 from HSPRG1 */
/* Blow away any reservation according to 970 errata after saving CR */
- stdcx. r1, 0, r1
-
- /* done with processor_area; re-enable MSR:RI */
- mfmsr r0
- ori r0, r0, MSR_RI@l
- mtmsrd r0
+ ldx r0, 0, r1
+ stdcx. r0, 0, r1
/* save CTR and use it to jump */
mfctr r0
@@ -147,6 +143,13 @@ 1:
li r0, -1 /* we clobbered the OS's SRR0/SRR1 to get here. */
std r0, UREGS_srr0(\uregs)
std r0, UREGS_srr1(\uregs)
+
+ /* done with processor_area; re-enable MSR:RI */
+ mfmsr r0
+ ori r0, r0, MSR_RI@l
+ mtmsrd r0
+
+
.endm
/* For exceptions that use HSRR0/1 (preserving the OS's SRR0/1). */
@@ -167,6 +170,12 @@ 1:
std r0, UREGS_srr0(\uregs)
mfspr r0, SPRN_SRR1
std r0, UREGS_srr1(\uregs)
+
+ /* done with processor_area; re-enable MSR:RI */
+ mfmsr r0
+ ori r0, r0, MSR_RI@l
+ mtmsrd r0
+
.endm
/* Hypervisor exception handling code; copied to physical address zero. */
@@ -374,6 +383,7 @@ ex_hcall_continued:
mfmsr r14
ori r14, r14, MSR_EE
xori r15, r14, MSR_EE
+
hcall_test_all_events:
mtmsrd r15, 1 /* disable interrupts */
ld r3, PAREA_vcpu(r13)
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