# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID c1d53788a25e07b4ac4ef49c3e3d76f7ad3f6b8f
# Parent 08aede767c63f7814cc89b97b277514a9f9644fc
Add support for XCHG instruction accessing LAPIC device model.
Signed-off-by: Boris Ostrovsky <bostrovsky@xxxxxxxxxxxxxxx>
diff -r 08aede767c63 -r c1d53788a25e xen/Rules.mk
--- a/xen/Rules.mk Wed Apr 5 14:00:42 2006
+++ b/xen/Rules.mk Wed Apr 5 14:42:01 2006
@@ -31,6 +31,9 @@
HDRS += $(wildcard $(BASEDIR)/include/public/*.h)
HDRS += $(wildcard $(BASEDIR)/include/asm-$(TARGET_ARCH)/*.h)
HDRS += $(wildcard
$(BASEDIR)/include/asm-$(TARGET_ARCH)/$(TARGET_SUBARCH)/*.h)
+HDRS += $(wildcard $(BASEDIR)/include/asm-$(TARGET_ARCH)/hvm/*.h)
+HDRS += $(wildcard $(BASEDIR)/include/asm-$(TARGET_ARCH)/hvm/svm/*.h)
+HDRS += $(wildcard $(BASEDIR)/include/asm-$(TARGET_ARCH)/hvm/vmx/*.h)
# Do not depend on auto-generated header files.
HDRS := $(subst
$(BASEDIR)/include/asm-$(TARGET_ARCH)/asm-offsets.h,,$(HDRS))
HDRS := $(subst $(BASEDIR)/include/xen/banner.h,,$(HDRS))
diff -r 08aede767c63 -r c1d53788a25e xen/arch/x86/hvm/intercept.c
--- a/xen/arch/x86/hvm/intercept.c Wed Apr 5 14:00:42 2006
+++ b/xen/arch/x86/hvm/intercept.c Wed Apr 5 14:42:01 2006
@@ -123,6 +123,16 @@
req->u.data = tmp1;
break;
+ case IOREQ_TYPE_XCHG:
+ /*
+ * Note that we don't need to be atomic here since VCPU is accessing
+ * its own local APIC.
+ */
+ tmp1 = read_handler(v, req->addr, req->size);
+ write_handler(v, req->addr, req->size, (unsigned long) req->u.data);
+ req->u.data = tmp1;
+ break;
+
default:
printk("error ioreq type for local APIC %x\n", req->type);
domain_crash_synchronous();
@@ -143,7 +153,7 @@
if ( hvm_mmio_handlers[i]->check_handler(v, p->addr) ) {
hvm_mmio_access(v, p,
hvm_mmio_handlers[i]->read_handler,
- hvm_mmio_handlers[i]->write_handler);
+ hvm_mmio_handlers[i]->write_handler);
return 1;
}
}
diff -r 08aede767c63 -r c1d53788a25e xen/arch/x86/hvm/platform.c
--- a/xen/arch/x86/hvm/platform.c Wed Apr 5 14:00:42 2006
+++ b/xen/arch/x86/hvm/platform.c Wed Apr 5 14:42:01 2006
@@ -439,6 +439,14 @@
GET_OP_SIZE_FOR_BYTE(size_reg);
return mem_reg(size_reg, opcode, instr, rex);
+ case 0x87: /* xchg {r/m16|r/m32}, {m/r16|m/r32} */
+ instr->instr = INSTR_XCHG;
+ GET_OP_SIZE_FOR_NONEBYTE(instr->op_size);
+ if (((*(opcode+1)) & 0xc7) == 5)
+ return reg_mem(instr->op_size, opcode, instr, rex);
+ else
+ return mem_reg(instr->op_size, opcode, instr, rex);
+
case 0x88: /* mov r8, m8 */
instr->instr = INSTR_MOV;
instr->op_size = BYTE;
@@ -936,6 +944,17 @@
break;
}
+ case INSTR_XCHG:
+ mmio_opp->flags = mmio_inst.flags;
+ mmio_opp->instr = mmio_inst.instr;
+ mmio_opp->operand[0] = mmio_inst.operand[0]; /* source */
+ mmio_opp->operand[1] = mmio_inst.operand[1]; /* destination */
+
+ /* send the request and wait for the value */
+ send_mmio_req(IOREQ_TYPE_XCHG, gpa, 1,
+ mmio_inst.op_size, 0, IOREQ_WRITE, 0);
+ break;
+
default:
printf("Unhandled MMIO instruction\n");
domain_crash_synchronous();
diff -r 08aede767c63 -r c1d53788a25e xen/include/asm-x86/hvm/io.h
--- a/xen/include/asm-x86/hvm/io.h Wed Apr 5 14:00:42 2006
+++ b/xen/include/asm-x86/hvm/io.h Wed Apr 5 14:42:01 2006
@@ -66,6 +66,7 @@
#define INSTR_STOS 10
#define INSTR_TEST 11
#define INSTR_BT 12
+#define INSTR_XCHG 13
struct instruction {
__s8 instr; /* instruction type */
diff -r 08aede767c63 -r c1d53788a25e xen/include/public/hvm/ioreq.h
--- a/xen/include/public/hvm/ioreq.h Wed Apr 5 14:00:42 2006
+++ b/xen/include/public/hvm/ioreq.h Wed Apr 5 14:42:01 2006
@@ -34,6 +34,7 @@
#define IOREQ_TYPE_AND 2
#define IOREQ_TYPE_OR 3
#define IOREQ_TYPE_XOR 4
+#define IOREQ_TYPE_XCHG 5
/*
* VMExit dispatcher should cooperate with instruction decoder to
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