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[Xen-changelog] - CONFIG_VTI=n by default.

To: xen-changelog@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-changelog] - CONFIG_VTI=n by default.
From: BitKeeper Bot <riel@xxxxxxxxxxx>
Date: Fri, 20 May 2005 16:43:37 +0000
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ChangeSet 1.1389.23.4, 2005/05/20 09:43:37-07:00, 
adsharma@xxxxxxxxxxxxxxxxxxxxxx

        - CONFIG_VTI=n by default.
        - Reorganize code such that the changes to cp_patch files are minimized
        
        Signed-off-by: Kevin Tian <kevin.tian@xxxxxxxxx>
        Signed-off-by: Arun Sharma <arun.sharma@xxxxxxxxx>



 arch/ia64/Rules.mk                       |    2 
 arch/ia64/mm_init.c                      |   14 --
 arch/ia64/patch/linux-2.6.11/page.h      |   15 --
 arch/ia64/patch/linux-2.6.11/processor.h |  177 +------------------------
 arch/ia64/patch/linux-2.6.11/system.h    |   64 +--------
 arch/ia64/vmx_init.c                     |   21 +++
 arch/ia64/xensetup.c                     |    6 
 include/asm-ia64/vmx.h                   |    3 
 include/asm-ia64/xenprocessor.h          |  213 +++++++++++++++++++++++++++++++
 include/asm-ia64/xensystem.h             |   63 +++++++++
 10 files changed, 328 insertions(+), 250 deletions(-)


diff -Nru a/xen/arch/ia64/Rules.mk b/xen/arch/ia64/Rules.mk
--- a/xen/arch/ia64/Rules.mk    2005-05-23 12:04:04 -04:00
+++ b/xen/arch/ia64/Rules.mk    2005-05-23 12:04:04 -04:00
@@ -1,7 +1,7 @@
 ########################################
 # ia64-specific definitions
 
-CONFIG_VTI     ?= y
+CONFIG_VTI     ?= n
 ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
 CROSS_COMPILE ?= /usr/local/sp_env/v2.2.5/i686/bin/ia64-unknown-linux-
 endif
diff -Nru a/xen/arch/ia64/mm_init.c b/xen/arch/ia64/mm_init.c
--- a/xen/arch/ia64/mm_init.c   2005-05-23 12:04:04 -04:00
+++ b/xen/arch/ia64/mm_init.c   2005-05-23 12:04:04 -04:00
@@ -301,20 +301,6 @@
                 pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)),
                 PERCPU_PAGE_SHIFT);
 
-#ifdef CONFIG_VTI
-       {
-               u64 base;
-               extern void vmx_switch_rr7(void);
-
-               base = (u64) &vmx_switch_rr7;
-               base = *((u64*)base);
-               ia64_itr(0x1, IA64_TR_RR7_SWITCH_STUB, XEN_RR7_SWITCH_STUB,
-                        pte_val(pfn_pte(__pa(base) >> PAGE_SHIFT, 
PAGE_KERNEL)),
-                        RR7_SWITCH_SHIFT);
-               printk("Add TR mapping for rr7 switch stub, with physical: 
0x%lx\n", (u64)(__pa(base)));
-       }
-#endif // CONFIG_VTI
-
        ia64_set_psr(psr);
        ia64_srlz_i();
 
diff -Nru a/xen/arch/ia64/patch/linux-2.6.11/page.h 
b/xen/arch/ia64/patch/linux-2.6.11/page.h
--- a/xen/arch/ia64/patch/linux-2.6.11/page.h   2005-05-23 12:04:04 -04:00
+++ b/xen/arch/ia64/patch/linux-2.6.11/page.h   2005-05-23 12:04:04 -04:00
@@ -1,17 +1,14 @@
---- 
/home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h
       2005-03-01 23:37:48.000000000 -0800
-+++ 
/home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/page.h
  2005-05-18 12:40:50.000000000 -0700
-@@ -32,6 +32,10 @@
+--- 
/home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h
        2005-03-01 23:37:48.000000000 -0800
++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/page.h   
2005-05-20 09:36:02.000000000 -0700
+@@ -32,6 +32,7 @@
  #define PAGE_ALIGN(addr)      (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
  
  #define PERCPU_PAGE_SHIFT     16      /* log2() of max. size of per-CPU area 
*/
-+#ifdef CONFIG_VTI
-+#define RR7_SWITCH_SHIFT      12      /* 4k enough */
-+#endif // CONFIG_VTI
 +
  #define PERCPU_PAGE_SIZE      (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
  
  #define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE)      /* per 
region addr limit */
-@@ -95,9 +99,15 @@
+@@ -95,9 +96,15 @@
  #endif
  
  #ifndef CONFIG_DISCONTIGMEM
@@ -27,7 +24,7 @@
  #else
  extern struct page *vmem_map;
  extern unsigned long max_low_pfn;
-@@ -109,6 +119,11 @@
+@@ -109,6 +116,11 @@
  #define page_to_phys(page)    (page_to_pfn(page) << PAGE_SHIFT)
  #define virt_to_page(kaddr)   pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
  
@@ -39,7 +36,7 @@
  typedef union ia64_va {
        struct {
                unsigned long off : 61;         /* intra-region offset */
-@@ -124,8 +139,23 @@
+@@ -124,8 +136,23 @@
   * expressed in this way to ensure they result in a single "dep"
   * instruction.
   */
@@ -63,7 +60,7 @@
  
  #define REGION_NUMBER(x)      ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
  #define REGION_OFFSET(x)      ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
-@@ -197,7 +227,11 @@
+@@ -197,7 +224,11 @@
  # define __pgprot(x)  (x)
  #endif /* !STRICT_MM_TYPECHECKS */
  
diff -Nru a/xen/arch/ia64/patch/linux-2.6.11/processor.h 
b/xen/arch/ia64/patch/linux-2.6.11/processor.h
--- a/xen/arch/ia64/patch/linux-2.6.11/processor.h      2005-05-23 12:04:04 
-04:00
+++ b/xen/arch/ia64/patch/linux-2.6.11/processor.h      2005-05-23 12:04:04 
-04:00
@@ -1,179 +1,30 @@
---- 
/home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h
  2005-03-01 23:37:58.000000000 -0800
-+++ 
/home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/processor.h
     2005-05-18 12:40:50.000000000 -0700
-@@ -131,9 +131,166 @@
-       __u64 ri : 2;
-       __u64 ed : 1;
+--- 
/home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h
   2005-03-01 23:37:58.000000000 -0800
++++ 
/home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/processor.h   
   2005-05-20 09:36:02.000000000 -0700
+@@ -94,7 +94,11 @@
+ #ifdef CONFIG_NUMA
+ #include <asm/nodedata.h>
+ #endif
++#ifdef XEN
++#include <asm/xenprocessor.h>
++#endif
+ 
++#ifndef XEN
+ /* like above but expressed as bitfields for more efficient access: */
+ struct ia64_psr {
+       __u64 reserved0 : 1;
+@@ -133,6 +137,7 @@
        __u64 bn : 1;
-+#ifdef CONFIG_VTI
-+      __u64 ia : 1;
-+      __u64 vm : 1;
-+      __u64 reserved5 : 17;
-+#else // CONFIG_VTI
        __u64 reserved4 : 19;
-+#endif // CONFIG_VTI
  };
++#endif
  
-+#ifdef  CONFIG_VTI
-+/* vmx like above but expressed as bitfields for more efficient access: */
-+typedef  union{
-+    __u64 val;
-+    struct{
-+      __u64 reserved0 : 1;
-+      __u64 be : 1;
-+      __u64 up : 1;
-+      __u64 ac : 1;
-+      __u64 mfl : 1;
-+      __u64 mfh : 1;
-+      __u64 reserved1 : 7;
-+      __u64 ic : 1;
-+      __u64 i : 1;
-+      __u64 pk : 1;
-+      __u64 reserved2 : 1;
-+      __u64 dt : 1;
-+      __u64 dfl : 1;
-+      __u64 dfh : 1;
-+      __u64 sp : 1;
-+      __u64 pp : 1;
-+      __u64 di : 1;
-+      __u64 si : 1;
-+      __u64 db : 1;
-+      __u64 lp : 1;
-+      __u64 tb : 1;
-+      __u64 rt : 1;
-+      __u64 reserved3 : 4;
-+      __u64 cpl : 2;
-+      __u64 is : 1;
-+      __u64 mc : 1;
-+      __u64 it : 1;
-+      __u64 id : 1;
-+      __u64 da : 1;
-+      __u64 dd : 1;
-+      __u64 ss : 1;
-+      __u64 ri : 2;
-+      __u64 ed : 1;
-+      __u64 bn : 1;
-+      __u64 reserved4 : 19;
-+    };
-+}   IA64_PSR;
-+
-+typedef union {
-+    __u64 val;
-+    struct {
-+        __u64 code : 16;
-+        __u64 vector : 8;
-+        __u64 reserved1 : 8;
-+        __u64 x : 1;
-+        __u64 w : 1;
-+        __u64 r : 1;
-+        __u64 na : 1;
-+        __u64 sp : 1;
-+        __u64 rs : 1;
-+        __u64 ir : 1;
-+        __u64 ni : 1;
-+        __u64 so : 1;
-+        __u64 ei : 2;
-+        __u64 ed : 1;
-+        __u64 reserved2 : 20;
-+    };
-+}   ISR;
-+
-+
-+typedef union {
-+    __u64 val;
-+    struct {
-+        __u64 ve : 1;
-+        __u64 reserved0 : 1;
-+        __u64 size : 6;
-+        __u64 vf : 1;
-+        __u64 reserved1 : 6;
-+        __u64 base : 49;
-+    };
-+}   PTA;
-+
-+typedef union {
-+    __u64 val;
-+    struct {
-+        __u64  rv  : 16;
-+        __u64  eid : 8;
-+        __u64  id  : 8;
-+        __u64  ig  : 32;
-+    };
-+} LID;
-+
-+typedef union{
-+    __u64 val;
-+    struct {
-+        __u64 rv  : 3;
-+        __u64 ir  : 1;
-+        __u64 eid : 8;
-+        __u64 id  : 8;
-+        __u64 ib_base : 44;
-+    };
-+} ipi_a_t;
-+
-+typedef union{
-+    __u64 val;
-+    struct {
-+        __u64 vector : 8;
-+        __u64 dm  : 3;
-+        __u64 ig  : 53;
-+    };
-+} ipi_d_t;
-+
-+
-+#define IA64_ISR_CODE_MASK0     0xf
-+#define IA64_UNIMPL_DADDR_FAULT     0x30
-+#define IA64_UNIMPL_IADDR_TRAP      0x10
-+#define IA64_RESERVED_REG_FAULT     0x30
-+#define IA64_REG_NAT_CONSUMPTION_FAULT  0x10
-+#define IA64_NAT_CONSUMPTION_FAULT  0x20
-+#define IA64_PRIV_OP_FAULT      0x10
-+
-+/* indirect register type */
-+enum {
-+    IA64_CPUID,     /*  cpuid */
-+    IA64_DBR,       /*  dbr */
-+    IA64_IBR,       /*  ibr */
-+    IA64_PKR,       /*  pkr */
-+    IA64_PMC,       /*  pmc */
-+    IA64_PMD,       /*  pmd */
-+    IA64_RR         /*  rr */
-+};
-+

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