ChangeSet 1.1423.5.2, 2005/05/06 15:20:51-06:00, djm@xxxxxxxxxxxxxxx
First implementation of hyperprivops (no fast assembly yet)
Signed-off by: Dan Magenheimer <dan.magenheimer@xxxxxx>
asm-offsets.c | 4 ++++
ivt.S | 14 +++++++++++++-
privop.c | 32 ++++++++++++++++++++++++++++++++
process.c | 4 ++++
vcpu.c | 12 ++++++++++++
5 files changed, 65 insertions(+), 1 deletion(-)
diff -Nru a/xen/arch/ia64/asm-offsets.c b/xen/arch/ia64/asm-offsets.c
--- a/xen/arch/ia64/asm-offsets.c 2005-05-11 03:03:44 -04:00
+++ b/xen/arch/ia64/asm-offsets.c 2005-05-11 03:03:44 -04:00
@@ -8,6 +8,7 @@
#include <xen/sched.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
+#include <public/xen.h>
#define task_struct exec_domain
@@ -37,6 +38,9 @@
BLANK();
+ DEFINE(XSI_PSR_IC_OFS, offsetof(vcpu_info_t,
arch.interrupt_collection_enabled));
+ DEFINE(XSI_PSR_IC, (SHAREDINFO_ADDR+offsetof(vcpu_info_t,
arch.interrupt_collection_enabled)));
+ DEFINE(XSI_PSR_I_OFS, offsetof(vcpu_info_t,
arch.interrupt_delivery_enabled));
//DEFINE(IA64_TASK_BLOCKED_OFFSET,offsetof (struct task_struct,
blocked));
//DEFINE(IA64_TASK_CLEAR_CHILD_TID_OFFSET,offsetof (struct task_struct,
clear_child_tid));
//DEFINE(IA64_TASK_GROUP_LEADER_OFFSET, offsetof (struct task_struct,
group_leader));
diff -Nru a/xen/arch/ia64/ivt.S b/xen/arch/ia64/ivt.S
--- a/xen/arch/ia64/ivt.S 2005-05-11 03:03:44 -04:00
+++ b/xen/arch/ia64/ivt.S 2005-05-11 03:03:44 -04:00
@@ -778,10 +778,22 @@
mov r17=cr.iim
mov r31=pr
;;
+ movl r18=XSI_PSR_IC
+ ;;
+ ld8 r19=[r18]
+ ;;
cmp.eq p7,p0=r0,r17 // is this a psuedo-cover?
- // FIXME: may also need to check slot==2?
(p7) br.sptk.many dispatch_privop_fault
+ ;;
+ cmp.ne p7,p0=r0,r19
+(p7) br.sptk.many dispatch_break_fault
+ // If we get to here, we have a hyperprivop
+ // For now, hyperprivops are handled through the break mechanism
+ // Later, they will be fast hand-coded assembly with psr.ic off
+ // which means no calls, no use of r1-r15 and no memory accesses
+ // except to pinned addresses!
br.sptk.many dispatch_break_fault
+ ;;
#endif
mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle
read lat.
mov r17=cr.iim
diff -Nru a/xen/arch/ia64/privop.c b/xen/arch/ia64/privop.c
--- a/xen/arch/ia64/privop.c 2005-05-11 03:03:44 -04:00
+++ b/xen/arch/ia64/privop.c 2005-05-11 03:03:44 -04:00
@@ -758,6 +758,38 @@
}
+// FIXME: Move these to include/public/arch-ia64?
+#define HYPERPRIVOP_RFI 1
+#define HYPERPRIVOP_RSM_DT 2
+#define HYPERPRIVOP_SSM_DT 3
+#define HYPERPRIVOP_COVER 4
+
+/* hyperprivops are generally executed in assembly (with physical psr.ic off)
+ * so this code is primarily used for debugging them */
+int
+ia64_hyperprivop(unsigned long iim)
+{
+ struct exec_domain *ed = (struct domain *) current;
+
+// FIXME: Add instrumentation for these
+ switch(iim) {
+ case HYPERPRIVOP_RFI:
+ (void)vcpu_rfi(ed);
+ return 0; // don't update iip
+ case HYPERPRIVOP_RSM_DT:
+ (void)vcpu_reset_psr_dt(ed);
+ return 1;
+ case HYPERPRIVOP_SSM_DT:
+ (void)vcpu_set_psr_dt(ed);
+ return 1;
+ case HYPERPRIVOP_COVER:
+ (void)vcpu_cover(ed);
+ return 1;
+ }
+ return 0;
+}
+
+
/**************************************************************************
Privileged operation instrumentation routines
**************************************************************************/
diff -Nru a/xen/arch/ia64/process.c b/xen/arch/ia64/process.c
--- a/xen/arch/ia64/process.c 2005-05-11 03:03:44 -04:00
+++ b/xen/arch/ia64/process.c 2005-05-11 03:03:44 -04:00
@@ -722,6 +722,10 @@
if (ia64_hypercall(regs))
vcpu_increment_iip(current);
}
+ else if (!PSCB(ed,interrupt_collection_enabled)) {
+ if (ia64_hyperprivop(iim))
+ vcpu_increment_iip(current);
+ }
else reflect_interruption(ifa,isr,iim,regs,IA64_BREAK_VECTOR);
}
diff -Nru a/xen/arch/ia64/vcpu.c b/xen/arch/ia64/vcpu.c
--- a/xen/arch/ia64/vcpu.c 2005-05-11 03:03:44 -04:00
+++ b/xen/arch/ia64/vcpu.c 2005-05-11 03:03:44 -04:00
@@ -120,6 +120,12 @@
}
}
+IA64FAULT vcpu_reset_psr_dt(VCPU *vcpu)
+{
+ vcpu_set_metaphysical_mode(vcpu,TRUE);
+ return IA64_NO_FAULT;
+}
+
IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24)
{
struct ia64_psr psr, imm, *ipsr;
@@ -153,6 +159,12 @@
extern UINT64 vcpu_check_pending_interrupts(VCPU *vcpu);
#define SPURIOUS_VECTOR 0xf
+
+IA64FAULT vcpu_set_psr_dt(VCPU *vcpu)
+{
+ vcpu_set_metaphysical_mode(vcpu,FALSE);
+ return IA64_NO_FAULT;
+}
IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24)
{
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