Bill Davidsen wrote:
Ralph Gauges wrote:
Hi,
I am currently trying to create a DomU to run an unmodified Linux
Distro Installer from CD. So far I have managed to get Xen 3.0.3
running on Debian Etch and I have created a configuration to run the
installer in a new virtual machine.
Now whenever I try to create the virtual machine with "xm create" I
get the following error message:
Error: HVM guest support is unavailable: is VT/AMD-V supported by
your CPU and enabled in your BIOS?
OK. This error message is rather obvious and actually the first time
it was right, VT was disabled in the BIOS, so I went and enabled VT
in the BIOS, but still when I try to create the virtual machine I get
this error message.
Can anybody give me some hint as to why Xen will not recognize VT
support?
Do I have to recompile xen after enabling VT in the BIOS? Or is the
Xeon 5130 just not supported in Xen 3.0.3 yet?
Could you post /proc/cpuinfo and the ACPI lines of dmesg?
Hi,
here is the output you asked for. Actually I managed to get everything
working as expected on my computer at home which has a similar CPU, so I
am going to repeat all the steps on this server and hope for the best. I
guess there is some issue with the Debian packages, although I don't
have a clue what it is.
Thanks a lot again for looking into this
Ralph
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Xeon(R) CPU 5130 @ 2.00GHz
stepping : 6
cpu MHz : 2000.212
cache size : 4096 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm
constant_tsc pni monitor ds_cpl vmx tm2 cx16 xtpr lahf_lm
bogomips : 4004.59
Mount-cache hash table entries: 512
CPU: After generic identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
CPU: After vendor identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
monitor/mwait feature present.
using mwait in idle threads.
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 4096K
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 0
CPU: After all inits, caps: bfebfbff 20100000 00000000 00000140 0004e33d
00000000 00000001
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
CPU0: Intel(R) Xeon(R) CPU 5130 @ 2.00GHz stepping 06
SMP alternatives: switching to SMP code
Booting processor 1/1 eip 3000
Initializing CPU#1
Calibrating delay using timer specific routine.. 4000.34 BogoMIPS
(lpj=8000680)
CPU: After generic identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
CPU: After vendor identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
monitor/mwait feature present.
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 4096K
CPU: Physical Processor ID: 0
CPU: Processor Core ID: 1
CPU: After all inits, caps: bfebfbff 20100000 00000000 00000140 0004e33d
00000000 00000001
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#1.
CPU1: Intel(R) Xeon(R) CPU 5130 @ 2.00GHz stepping 06
SMP alternatives: switching to SMP code
Booting processor 2/6 eip 3000
Initializing CPU#2
Calibrating delay using timer specific routine.. 4000.30 BogoMIPS
(lpj=8000619)
CPU: After generic identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
CPU: After vendor identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
monitor/mwait feature present.
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 4096K
CPU: Physical Processor ID: 3
CPU: Processor Core ID: 0
CPU: After all inits, caps: bfebfbff 20100000 00000000 00000140 0004e33d
00000000 00000001
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#2.
CPU2: Intel(R) Xeon(R) CPU 5130 @ 2.00GHz stepping 06
SMP alternatives: switching to SMP code
Booting processor 3/7 eip 3000
Initializing CPU#3
Calibrating delay using timer specific routine.. 4000.36 BogoMIPS
(lpj=8000731)
CPU: After generic identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
CPU: After vendor identify, caps: bfebfbff 20100000 00000000 00000000
0004e33d 00000000 00000001
monitor/mwait feature present.
CPU: L1 I cache: 32K, L1 D cache: 32K
CPU: L2 cache: 4096K
CPU: Physical Processor ID: 3
CPU: Processor Core ID: 1
CPU: After all inits, caps: bfebfbff 20100000 00000000 00000140 0004e33d
00000000 00000001
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#3.
CPU3: Intel(R) Xeon(R) CPU 5130 @ 2.00GHz stepping 06
Total of 4 processors activated (16005.61 BogoMIPS).
ENABLING IO-APIC IRQs
..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1
checking TSC synchronization across 4 CPUs: passed.
Brought up 4 CPUs
_______________________________________________
Xen-users mailing list
Xen-users@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-users
|
Home