[XEN][POWERPC][PATCH 1/3] Guest Perfmon implementation - structures,
initializations, context switches
->attachment
--
Grüsse / regards,
Christian Ehrhardt
IBM Linux Technology Center, Open Virtualization
+49 7031/16-3385
Ehrhardt@xxxxxxxxxxxxxxxxxxx
Ehrhardt@xxxxxxxxxx
IBM Deutschland Entwicklung GmbH
Vorsitzender des Aufsichtsrats: Johann Weihen
Geschäftsführung: Herbert Kircher
Sitz der Gesellschaft: Böblingen
Registergericht: Amtsgericht Stuttgart, HRB 243294
# HG changeset patch
# User Christian Ehrhardt <ehrhardt@xxxxxxxxxxxxxxxxxx>
# Date 1178508863 -7200
# Node ID c3dc8f02bf0ebb4ce277096a8fd966f59cf7e7fe
# Parent 3a5722420de74aafbe3e11e0faad501c7babe3e4
[XEN][POWERPC][PATCH 1/3] Guest Perfmon implementation - structures,
initializations, context switches
This is the first step of enabling oprofile performance monitoring on the
xenppc platform. It allows users to work with oprofile in Dom0 and DomU guests
as known from non virtualized ppc-linux.
This patch:
- adds the needed structures and flags to arch_vcpu
- implement needed context switch actions dependent on the per domain flag
Signed-off-by: Christian Ehrhardt <ehrhardt@xxxxxxxxxxxxxxxxxx>
diff -r 3a5722420de7 -r c3dc8f02bf0e xen/arch/powerpc/domain.c
--- a/xen/arch/powerpc/domain.c Thu May 03 19:25:47 2007 +0100
+++ b/xen/arch/powerpc/domain.c Mon May 07 05:34:23 2007 +0200
@@ -144,6 +144,21 @@ int vcpu_initialise(struct vcpu *v)
{
/* Guests by default have a 100Hz ticker. */
v->periodic_period = MILLISECS(10);
+ v->arch.pmu_enabled = 0;
+ v->arch.perf_sprs_stored = 0;
+ v->arch.perf_sprs.mmcr0 = 0;
+ v->arch.perf_sprs.mmcr1 = 0;
+ v->arch.perf_sprs.mmcra = 0;
+ v->arch.perf_sprs.pmc[0] = 0;
+ v->arch.perf_sprs.pmc[1] = 0;
+ v->arch.perf_sprs.pmc[2] = 0;
+ v->arch.perf_sprs.pmc[3] = 0;
+ v->arch.perf_sprs.pmc[4] = 0;
+ v->arch.perf_sprs.pmc[5] = 0;
+#ifdef CONFIG_PPC64
+ v->arch.perf_sprs.pmc[6] = 0;
+ v->arch.perf_sprs.pmc[7] = 0;
+#endif
return 0;
}
diff -r 3a5722420de7 -r c3dc8f02bf0e xen/arch/powerpc/powerpc64/domain.c
--- a/xen/arch/powerpc/powerpc64/domain.c Thu May 03 19:25:47 2007 +0100
+++ b/xen/arch/powerpc/powerpc64/domain.c Mon May 07 05:34:23 2007 +0200
@@ -22,7 +22,42 @@
#include <xen/lib.h>
#include <xen/sched.h>
#include <xen/mm.h>
+#include <xen/domain.h>
#include <asm/current.h>
+
+inline void save_pmc_sprs(perf_sprs_t *p_sprs)
+{
+ p_sprs->mmcr0 = mfmmcr0();
+ p_sprs->mmcr1 = mfmmcr1();
+ p_sprs->mmcra = mfmmcra();
+ p_sprs->pmc[0] = mfpmc1();
+ p_sprs->pmc[1] = mfpmc2();
+ p_sprs->pmc[2] = mfpmc3();
+ p_sprs->pmc[3] = mfpmc4();
+ p_sprs->pmc[4] = mfpmc5();
+ p_sprs->pmc[5] = mfpmc6();
+#ifdef CONFIG_PPC64
+ p_sprs->pmc[6] = mfpmc7();
+ p_sprs->pmc[7] = mfpmc8();
+#endif
+}
+
+inline void load_pmc_sprs(perf_sprs_t *p_sprs)
+{
+ mtpmc1(p_sprs->pmc[0]);
+ mtpmc2(p_sprs->pmc[1]);
+ mtpmc3(p_sprs->pmc[2]);
+ mtpmc4(p_sprs->pmc[3]);
+ mtpmc5(p_sprs->pmc[4]);
+ mtpmc6(p_sprs->pmc[5]);
+#ifdef CONFIG_PPC64
+ mtpmc7(p_sprs->pmc[6]);
+ mtpmc8(p_sprs->pmc[7]);
+#endif
+ mtmmcra(p_sprs->mmcra);
+ mtmmcr1(p_sprs->mmcr1);
+ mtmmcr0(p_sprs->mmcr0);
+}
void save_sprs(struct vcpu *v)
{
@@ -35,6 +70,11 @@ void save_sprs(struct vcpu *v)
v->arch.dar = mfdar();
v->arch.dsisr = mfdsisr();
+
+ if (v->arch.pmu_enabled) {
+ save_pmc_sprs(&(v->arch.perf_sprs));
+ v->arch.perf_sprs_stored = 1;
+ }
save_cpu_sprs(v);
}
@@ -49,6 +89,15 @@ void load_sprs(struct vcpu *v)
mtsprg3(v->arch.sprg[3]);
mtdar(v->arch.dar);
mtdsisr(v->arch.dsisr);
+
+ if (v->arch.pmu_enabled) {
+ if (v->arch.perf_sprs_stored) {
+ load_pmc_sprs(&(v->arch.perf_sprs));
+ }
+ else {
+ load_pmc_sprs(&perf_clear_sprs);
+ }
+ }
load_cpu_sprs(v);
diff -r 3a5722420de7 -r c3dc8f02bf0e xen/include/asm-powerpc/domain.h
--- a/xen/include/asm-powerpc/domain.h Thu May 03 19:25:47 2007 +0100
+++ b/xen/include/asm-powerpc/domain.h Mon May 07 05:34:23 2007 +0200
@@ -29,6 +29,17 @@
#include <public/arch-powerpc.h>
#include <asm/htab.h>
#include <asm/powerpc64/ppc970.h>
+
+
+typedef struct {
+ ulong mmcr0;
+ ulong mmcr1;
+ ulong mmcra;
+ ulong pmc[NUM_PMCS];
+} perf_sprs_t;
+
+extern atomic_t perf_count_active;
+extern perf_sprs_t perf_clear_sprs;
struct arch_domain {
struct domain_htab htab;
@@ -84,7 +95,12 @@ struct arch_vcpu {
ulong timebase;
ulong dar;
ulong dsisr;
-
+
+ /* performance monitor sprs per vcpu */
+ int pmu_enabled;
+ int perf_sprs_stored;
+ perf_sprs_t perf_sprs;
+
/* Segment Lookaside Buffer */
struct slb_entry slb_entries[NUM_SLB_ENTRIES];
@@ -100,6 +116,8 @@ struct arch_vcpu {
extern void full_resume(void);
+extern void save_pmc_sprs(perf_sprs_t *p_sprs);
+extern void load_pmc_sprs(perf_sprs_t *p_sprs);
extern void save_sprs(struct vcpu *);
extern void load_sprs(struct vcpu *);
extern void save_segments(struct vcpu *);
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