# HG changeset patch
# User Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
# Node ID e0bb62683805bc0dcd6ca5198b140f5910dbd358
# Parent f48cd49f4ee21fc44ef2fd85553c8c2008da8489
[XEN][POWERPC] Machine check now inspects the SCOM for more information
Also fixes suggested by <segher@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
---
xen/arch/powerpc/powerpc64/ppc970_machinecheck.c | 7 +++
xen/arch/powerpc/powerpc64/ppc970_scom.c | 41 ++++++++++-------------
2 files changed, 25 insertions(+), 23 deletions(-)
diff -r f48cd49f4ee2 -r e0bb62683805
xen/arch/powerpc/powerpc64/ppc970_machinecheck.c
--- a/xen/arch/powerpc/powerpc64/ppc970_machinecheck.c Thu Sep 21 13:48:24
2006 -0400
+++ b/xen/arch/powerpc/powerpc64/ppc970_machinecheck.c Fri Sep 22 11:02:47
2006 -0400
@@ -24,6 +24,8 @@
#include <public/xen.h>
#include <asm/processor.h>
#include <asm/percpu.h>
+#include <asm/debugger.h>
+#include "scom.h"
#define MCK_SRR1_INSN_FETCH_UNIT 0x0000000000200000 /* 42 */
#define MCK_SRR1_LOAD_STORE 0x0000000000100000 /* 43 */
@@ -54,6 +56,8 @@ int cpu_machinecheck(struct cpu_user_reg
if (mck_cpu_stats[mfpir()] != 0)
printk("While in CI IO\n");
+ show_backtrace_regs(regs);
+
printk("SRR1: 0x%016lx\n", regs->msr);
if (regs->msr & MCK_SRR1_INSN_FETCH_UNIT)
printk("42: Exception caused by Instruction Fetch Unit (IFU)\n"
@@ -67,6 +71,7 @@ int cpu_machinecheck(struct cpu_user_reg
case 0:
printk("0b00: Likely caused by an asynchronous machine check,\n"
" see SCOM Asynchronous Machine Check Register\n");
+ cpu_scom_AMCR();
break;
case MCK_SRR1_CAUSE_SLB_PAR:
printk("0b01: Exception caused by an SLB parity error detected\n"
@@ -116,5 +121,5 @@ int cpu_machinecheck(struct cpu_user_reg
dump_segments(0);
}
- return 0; /* for now lets not recover; */
+ return 0; /* for now lets not recover */
}
diff -r f48cd49f4ee2 -r e0bb62683805 xen/arch/powerpc/powerpc64/ppc970_scom.c
--- a/xen/arch/powerpc/powerpc64/ppc970_scom.c Thu Sep 21 13:48:24 2006 -0400
+++ b/xen/arch/powerpc/powerpc64/ppc970_scom.c Fri Sep 22 11:02:47 2006 -0400
@@ -24,6 +24,7 @@
#include <xen/console.h>
#include <xen/errno.h>
#include <asm/delay.h>
+#include "scom.h"
#define SPRN_SCOMC 276
#define SPRN_SCOMD 277
@@ -48,7 +49,7 @@ union scomc {
};
-static inline int read_scom(uint addr, ulong *d)
+int cpu_scom_read(uint addr, ulong *d)
{
union scomc c;
ulong flags;
@@ -56,9 +57,9 @@ static inline int read_scom(uint addr, u
/* drop the low 8bits (including parity) */
addr >>= 8;
- /* these give iface errors because the address is ambiguous after
- * the above bit dropping */
- BUG_ON(addr == 0x8000);
+ /* these give iface errors because the addresses are not software
+ * accessible */
+ BUG_ON(addr & 0x8000);
for (;;) {
c.word = 0;
@@ -100,7 +101,7 @@ static inline int read_scom(uint addr, u
}
}
-static inline int write_scom(uint addr, ulong d)
+int cpu_scom_write(uint addr, ulong d)
{
union scomc c;
ulong flags;
@@ -108,9 +109,9 @@ static inline int write_scom(uint addr,
/* drop the low 8bits (including parity) */
addr >>= 8;
- /* these give iface errors because the address is ambiguous after
- * the above bit dropping */
- BUG_ON(addr == 0x8000);
+ /* these give iface errors because the addresses are not software
+ * accessible */
+ BUG_ON(addr & 0x8000);
for (;;) {
c.word = 0;
@@ -150,25 +151,21 @@ static inline int write_scom(uint addr,
}
}
-/* SCOMC addresses are 16bit but we are given 24 bits in the
- * books. The low oerder 8 bits are some kinda parity thin and should
- * be ignored */
-#define SCOM_AMCS_REG 0x022601
-#define SCOM_AMCS_AND_MASK 0x022700
-#define SCOM_AMCS_OR_MASK 0x022800
-#define SCOM_CMCE 0x030901
-#define SCOM_PMCR 0x400801
-#define SCOM_PTSR 0x408001
-
-/* cannot access these since only top 16bits are considered */
-#define SCOM_STATUS 0x800003
-
void cpu_scom_init(void)
{
ulong val;
console_start_sync();
- if (!read_scom(SCOM_PTSR, &val))
+ if (!cpu_scom_read(SCOM_PTSR, &val))
printk("SCOM PTSR: 0x%016lx\n", val);
console_end_sync();
}
+
+void cpu_scom_AMCR(void)
+{
+ ulong val;
+
+ cpu_scom_read(SCOM_AMC_REG, &val);
+ printk("SCOM AMCR: 0x%016lx\n", val);
+}
+
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