Although I believe that tpa in vmx_dirty_bit never generate
a nested dtlb miss, this patch ensures the fault case.
I confirmed the additional code in this patch works fine
by means of a debugger. ;-)
Signed-off-by: Kouya Shimura <kouya@xxxxxxxxxxxxxx>
diff -r 29faad225cbb xen/arch/ia64/vmx/vmx_ivt.S
--- a/xen/arch/ia64/vmx/vmx_ivt.S Thu Feb 14 12:37:15 2008 -0700
+++ b/xen/arch/ia64/vmx/vmx_ivt.S Fri Feb 15 14:15:48 2008 +0900
@@ -410,6 +410,11 @@ END(vmx_alt_dtlb_miss)
// 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
ENTRY(vmx_nested_dtlb_miss)
VMX_DBG_FAULT(5)
+ mov r29=cr.ipsr
+ mov b0=r30
+ ;;
+ tbit.z p6,p0=r29,IA64_PSR_VM_BIT
+(p6)br.sptk b0 // return to the continuation point
VMX_FAULT(5)
END(vmx_nested_dtlb_miss)
@@ -433,16 +438,42 @@ END(vmx_dkey_miss)
/////////////////////////////////////////////////////////////////////////////////////////
// 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
ENTRY(vmx_dirty_bit)
- mov r29=cr.ipsr
+ VMX_DBG_FAULT(8)
+ mov r28=cr.ipsr
mov r31=pr
;;
mov r19=cr.ifa
- tbit.z p6,p0=r29,IA64_PSR_VM_BIT
-(p6)br.spnt.many vmx_fault_8
- ;;
- tpa r19=r19
+ tbit.z p6,p0=r28,IA64_PSR_VM_BIT
+(p6)br.spnt.few vmx_fault_8
+ // Prepare for nested dtlb miss
+ mov r22=b0
+ dep.z r29=r28,IA64_PSR_VM_BIT,1
+ ;;
+ mov cr.ipsr=r29 // ipsr.vm=0
+ movl r30=dirty_bit_tpa_fail
+ ;;
+ tpa r19=r19 // possibly nested dtlb miss?
+ mov cr.ipsr=r28 // ipsr.vm=1
br.sptk vmx_dispatch_shadow_fault
VMX_FAULT(8)
+dirty_bit_tpa_fail:
+ // Resume & Retry
+ mov cr.ipsr=r28 // ipsr.vm=1
+ mov r17=cr.isr
+ mov r23=r31
+// mov r22=b0 // b0 is clobbered in vmx_nested_dtlb_miss
+ adds r16=IA64_VPD_BASE_OFFSET,r21
+ ;;
+ ld8 r18=[r16]
+ ;;
+ adds r19=VPD(VPSR),r18
+ movl r20=__vsa_base
+ ;;
+ ld8 r19=[r19]
+ ld8 r20=[r20]
+ ;;
+ br.sptk ia64_vmm_entry
+ ;;
END(vmx_dirty_bit)
.org vmx_ia64_ivt+0x2400
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