[Xen-ia64-devel] metaphysical mode

["Magenheimer, Dan (HP Labs Fort Collins)" <dan.magenheimer@xxxxxx>]

Anthony's recent proposed patch reminded me of some
documentation about metaphysical mode that I had written
some time ago.  I thought I had sent this out, but
could not find it on the list, so I cleaned it up
a bit and am sending it out now.  This isn't intended
to imply that the design/implementation is cast in stone,
just to describe the intent.

Dan

===============

Paravirtualization allows us to slightly modify an architecture
to disallow or change the semantics for certain operations in
order to obtain a substantial performance gain.  One usage of
paravirtualization on Xen/ia64 involves the usage of physical
addressing:

There are three translation bits in IPF's psr to determine whether
an address to be used is physical or virtual, one bit each to
control instruction access, data access, and register stack
access, respectively psr.it, psr.dt, and psr.rt.  Some
combinations of these bits can be very difficult to
fully virtualize with adequate performance; an IPF
OS executes physical accesses frequently enough that trapping
every physical access (and possibly emulating physical
instruction accesses) is too slow.  Ideally, we would like
to allow guest physical addresses to be translated to machine
addresses using the existing virtual addressing hardware
and mechanisms.

The resulting implementation on Xen/ia64 (heavily leveraged
from the HP vBlades project) is called metaphysical memory.
When a guest enters "metaphysical mode", the physical psr
it/dt/rt bits remain set (virtual addressing) and region
register 0 is changed to use a per-guest reserved region id.

The implementation of metaphysical mode has some ramifications.
When metaphysical=1:
- all guest accesses in region 0 are accesses to (meta)physical
  memory
- guest data accesses outside of region 0 are also accesses
  to metaphysical memory, but since no guest will be assigned
  physical memory with an address that large, all data accesses
  outside of region 0 will result in a [TBD] fault
- instruction data accesses outside of region 0 are executed
  as if they are virtual accesses
- a guest may not set all combinations of the psr it/dt/rt bits.
  Attempts to set these combinations results in a Reserved
  register/field fault [note: not currently implemented]

        idr     <--psr.it, psr.dt, psr.rt
        000     metaphysical mode
        001     not permitted
        010     not permitted
        011     not currently permitted [should it be?]
        100     metaphysical mode
        101     not permitted
        110     not permitted
        111     virtual mode (metaphysical=0)

- reads of psr.it/dt/rt (mov psr.l= instruction) may not reflect
  the bits that were last set
- delivery of an interruption does not change the state of
  metaphysical mode and ipsr.it/dt/rt bits are set to [???]

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