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xen-devel
[Xen-devel] [PATCH] Eliminate cache flushing when entering C3 on select
AMD Fam15h processors have a shared cache. It does not need
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.
Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>
diff -r 510d84507f6b xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c Fri Jun 10 10:53:11 2011 -0500
+++ b/xen/arch/x86/acpi/cpu_idle.c Fri Jun 10 11:10:05 2011 -0500
@@ -549,7 +549,8 @@
flags->bm_check = 0;
if ( num_online_cpus() == 1 )
flags->bm_check = 1;
- else if ( c->x86_vendor == X86_VENDOR_INTEL )
+ else if ( ( c->x86_vendor == X86_VENDOR_INTEL ) ||
+ ( ( c->x86_vendor == X86_VENDOR_AMD ) && ( c->x86 == 0x15 ) ) )
{
/*
* Today all MP CPUs that support C3 share cache.
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