WARNING - OLD ARCHIVES

This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
   
 
 
Xen 
 
Home Products Support Community News
 
   
 

xen-devel

[Xen-devel] [PATCH] Eliminate cache flushing when entering C3 on select

To: "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: [Xen-devel] [PATCH] Eliminate cache flushing when entering C3 on select AMD processors
From: "Langsdorf, Mark" <mark.langsdorf@xxxxxxx>
Date: Mon, 13 Jun 2011 09:56:26 -0500
Accept-language: en-US
Acceptlanguage: en-US
Cc: "Ostrovsky, Boris" <Boris.Ostrovsky@xxxxxxx>, 'andrew thomas' <andrew.thomas@xxxxxxxxxx>
Delivery-date: Mon, 13 Jun 2011 08:00:47 -0700
Envelope-to: www-data@xxxxxxxxxxxxxxxxxxx
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Thread-index: AcwnxGt6Nem9nP+WRniO5OZQqtlsiACFXgFQ
Thread-topic: [PATCH] Eliminate cache flushing when entering C3 on select AMD processors
AMD Fam15h processors have a shared cache. It does not need 
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>

diff -r 510d84507f6b xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c      Fri Jun 10 10:53:11 2011 -0500
+++ b/xen/arch/x86/acpi/cpu_idle.c      Fri Jun 10 11:10:05 2011 -0500
@@ -549,7 +549,8 @@
     flags->bm_check = 0;
     if ( num_online_cpus() == 1 )
         flags->bm_check = 1;
-    else if ( c->x86_vendor == X86_VENDOR_INTEL )
+    else if ( ( c->x86_vendor == X86_VENDOR_INTEL ) ||
+              ( ( c->x86_vendor == X86_VENDOR_AMD ) && ( c->x86 == 0x15 ) ) )
     {
         /*
          * Today all MP CPUs that support C3 share cache.      

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-devel

<Prev in Thread] Current Thread [Next in Thread>
  • [Xen-devel] [PATCH] Eliminate cache flushing when entering C3 on select AMD processors, Langsdorf, Mark <=