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xen-devel
RE: [Xen-devel] Constant vs Nonstop vs Invariant TSC question
Hi Roger –
Check out docs/misc/tscmode in the xen tree for some of this
detail.
Invariant TSC only appears on Nehalem-and-later Intel processors (also most modern
AMD processors). Constant doesn’t mean invariant (across processors), but
constant+nonstop is essentially the same thing, provided the BIOS syncs them at
boot and you don’t have multiple motherboards or hot-add processors etc.
Some Core2 Duos (Conroe) are constant+nonstop, others (Merom)
are not. However, some Conroes I think have a weird C-state that makes TSC
stop. To force a constant processor to also be non-stop, try the max_cstate=0
Xen boot parameter.
Hope that helps!
Dan
From: Roger Cruz
[mailto:roger.cruz@xxxxxxxxxxxxxxxxxxx]
Sent: Friday, September 17, 2010 1:32 PM
To: xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-devel] Constant vs Nonstop vs Invariant TSC question
From
/xen-unstable.hg/xen/arch/x86/cpu/intel.c
if ((c->x86 == 0xf &&
c->x86_model >= 0x03) ||
(c->x86 == 0x6 &&
c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC,
c->x86_capability);
if (cpuid_edx(0x80000007) &
(1u<<8)) {
set_bit(X86_FEATURE_CONSTANT_TSC,
c->x86_capability);
set_bit(X86_FEATURE_NONSTOP_TSC,
c->x86_capability);
set_bit(X86_FEATURE_TSC_RELIABLE,
c->x86_capability);
}
I am trying to determine the difference between the constant vs nonstop vs
invariant TSCs in newer processors. I understand constant tsc means the
rate of the counter won't vary if the CPU freq changes and non-stop means that
it even continues to count when the cpu is in a low power state.
When I read Intel's Designer's vol3b, section 16.11.1 Invariant TSC it
says the following
"16.11.1 Invariant TSC
The time stamp counter in newer processors may support an enhancement, referred
to as invariant TSC. Processor’s support for invariant TSC is indicated by
CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states.
This is the architectural behavior moving forward. On processors with invariant
TSC support, the OS may use the TSC for wall clock timer services (instead of
ACPI or HPET timers). TSC reads are much more efficient and do not incur the
overhead associated with a ring transition or access to a platform
resource."
So the first question "is a constant_tsc the same as Intel's
invariant_tsc or is an invariant_tsc the xen combination of both constant_tsc +
nonstop_tsc?" Based on the examination of the code, it appears to me
that it is the latter. Is this true?
I have a laptop with the Intel Centrino chipset, Intel Core 2 Duo, P8400,
2.26GHz and the CPUID(0x80000007) is returning a 0, indicating the TSC stops
while in low power states. I was under the impression that all Core 2
duos supported the invariant TSC but it doesn't look that way based on the
cpuid. Just want to hear confirmation from others with a similar chip
that they also lack the invariant tsc support.
Thanks
Roger R. Cruz
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