Re: [Xen-devel] sse, mmx support for hvm guests

["Ashish Bijlani" <ashish.bijlani@xxxxxxxxx>]

Hi,

i'm working on a project that requires migration of a VM from a
sse/mmx capable x86 platform to an x86 platform without sse/mmx
capability. i want to emulate sse/mmu capability at runtime. one
option would be to let the hypervisor emulate sse/mmx functionality
upon trapping due to illegal instruction exception. however, i
believe. this would be really slow and defeats the purpose of sse/mmx.
i can take the emulation code from qemu/bochs. any idea on what could
be a better option in terms of performance? also, i'd like to know if
this is reasonble at all or am i missing something?

thanks,
ashish

On Sun, Oct 26, 2008 at 4:36 AM, Keir Fraser <keir.fraser@xxxxxxxxxxxxx> wrote:
> Masking from CPUID should work. I'm surprised it would cause a guest to fail
> to boot.
>
>  K.
>
> On 25/10/08 23:30, "Ashish Bijlani" <ashish.bijlani@xxxxxxxxx> wrote:
>
>> it's just masking the sse/mmx features from cpuid return value or
>> something more to it? because i tried masking sse/mmx features from
>> cpuid and now the hvm domain doesn't boot!! any idea if sse/mmx
>> support can be disabled using bios?
>>
>> Thanks,
>> Ashish
>>
>> On Sat, Oct 25, 2008 at 7:13 PM, Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
>> wrote:
>>> On 25/10/08 20:34, "Ashish Bijlani" <ashish.bijlani@xxxxxxxxx> wrote:
>>>
>>>> I've a quad-core x86_64 machine (Intel Xeon), with sse/mmx support.
>>>> However, I want to disable sse/mmx support from HVM guests. How can I
>>>> do this? Also, is it reasonable to expect illegal instruction fault in
>>>> non-root VMX mode if a guest VM runs an application with sse/mmx
>>>> instructions?
>>>
>>> You can hide SSE/MMX in CPUID info, so the guest should not attempt to use
>>> the instructions. This is obviously true since CPUID causes vmexit and then
>>> the instruction is always emulated. But I don't think you can make the
>>> sse/mmx instructions fault if the guest does actually try to use them
>>> anyway.
>>>
>>>  -- Keir
>>>
>>>
>>>
>
>
>

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