[Xen-devel] [PATCH] NextRIPS support for forthcoming AMD processors

[Mark Langsdorf <mark.langsdorf@xxxxxxx>]

Future versions of AMD processors will support a feature called
NextRIPS or Next RIP Save.  This feature causes the processor
to store the next sequential RIP of a guest in the VMCB on
most instruction interrupts.  The hypervisor can use this 
information to determine how much memory to read to determine
the intercepted instruction, modestly improving performance.
The following patch implements support for this feature.

This patch has been stress tested at AMD for three weeks of
continuous runtime and should not cause any regressions.

-Mark Langsdorf
Operating System Research Center
AMD

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>

diff -r dbac9ee4d761 xen/arch/x86/hvm/svm/emulate.c
--- a/xen/arch/x86/hvm/svm/emulate.c    Mon Sep 08 16:02:13 2008 +0100
+++ b/xen/arch/x86/hvm/svm/emulate.c    Tue Sep 09 12:23:22 2008 -0500
@@ -61,6 +61,43 @@ static unsigned long svm_rip2pointer(str
     return p;
 }
 
+/* testing NextRIPS feature */
+int opt_nextrip_enabled = 1;
+
+boolean_param("nrip", opt_nextrip_enabled);
+
+static unsigned long svm_nextrip_is_valid(struct vcpu *v)
+{
+    struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
+    bool_t enabled = opt_nextrip_enabled && 
+        (svm_feature_flags & (1<<SVM_FEATURE_NRIPS));
+
+    if ((!enabled) || (vmcb->nextrip == 0) ||
+        (vmcb->nextrip <= vmcb->rip))
+        return 0; 
+
+    switch (vmcb->exitcode)
+    {
+    case VMEXIT_CR0_READ... VMEXIT_DR15_WRITE:
+        /* faults due to instruction intercepts */
+        /* (exitcodes 84-95) are reserved */
+    case VMEXIT_IDTR_READ ... VMEXIT_TR_WRITE:
+    case VMEXIT_RDTSC ... VMEXIT_SWINT:
+    case VMEXIT_INVD ... VMEXIT_INVLPGA:
+    case VMEXIT_VMRUN ...  VMEXIT_MWAIT_CONDITIONAL:
+    case VMEXIT_IOIO:
+        /* ...and the rest of the #VMEXITs */
+    case VMEXIT_CR0_SEL_WRITE:
+    case VMEXIT_MSR:
+    case VMEXIT_EXCEPTION_BP:
+       return 1;       
+        break;
+    default:
+        return 0;
+    }
+  
+    return 0;
+}
 /* First byte: Length. Following bytes: Opcode bytes. */
 #define MAKE_INSTR(nm, ...) static const u8 OPCODE_##nm[] = { __VA_ARGS__ }
 MAKE_INSTR(INVD,   2, 0x0f, 0x08);
@@ -118,6 +155,9 @@ int __get_instruction_length_from_list(s
     unsigned long fetch_addr;
     unsigned int fetch_len;
 
+    if (svm_nextrip_is_valid(v))
+        return (vmcb->nextrip - vmcb->rip);
+
     /* Fetch up to the next page break; we'll fetch from the next page
      * later if we have to. */
     fetch_addr = svm_rip2pointer(v);
diff -r dbac9ee4d761 xen/include/asm-x86/hvm/svm/vmcb.h
--- a/xen/include/asm-x86/hvm/svm/vmcb.h        Mon Sep 08 16:02:13 2008 +0100
+++ b/xen/include/asm-x86/hvm/svm/vmcb.h        Tue Sep 09 12:14:18 2008 -0500
@@ -393,7 +393,9 @@ struct vmcb_struct {
     eventinj_t  eventinj;       /* offset 0xA8 */
     u64 h_cr3;                  /* offset 0xB0 */
     lbrctrl_t lbr_control;      /* offset 0xB8 */
-    u64 res09[104];             /* offset 0xC0 pad to save area */
+    u64 res09;                 /* offset 0xC0 */
+    u64 nextrip;               /* offset 0xC8 */
+    u64 res10a[102];            /* offset 0xC0 pad to save area */
 
     svm_segment_register_t es;      /* offset 1024 */
     svm_segment_register_t cs;


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