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xen-devel
Re: [Xen-devel] RE: [Question] Do we need to support devices that do not
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To: |
"Shan, Haitao" <haitao.shan@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx> |
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Subject: |
Re: [Xen-devel] RE: [Question] Do we need to support devices that do not strictly follow the PCI-e specification? |
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From: |
Keir Fraser <keir.fraser@xxxxxxxxxxxxx> |
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Date: |
Thu, 09 Oct 2008 10:49:14 +0100 |
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Cc: |
"Tian, Kevin" <kevin.tian@xxxxxxxxx>, "Jiang, Yunhong" <yunhong.jiang@xxxxxxxxx>, "Huang, Zhiteng" <zhiteng.huang@xxxxxxxxx>, "Li, Xin B" <xin.b.li@xxxxxxxxx> |
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[Xen-devel] RE: [Question] Do we need to support devices that do not strictly follow the PCI-e specification? |
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Will do.
K.
On 9/10/08 10:31, "Shan, Haitao" <haitao.shan@xxxxxxxxx> wrote:
Hi, Keir,
There is already a fix for calculating the size of PCI-e capability properly. The changeset is 77fba269. But this changeset is not in xen-3.3-testing. Can you help to check in that changeset to xen-3.3-testing tree?
Thanks!
Shan Haitao
From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Shan, Haitao
Sent: 2008年10月9日 17:08
To: Keir Fraser; xen-devel@xxxxxxxxxxxxxxxxxxx
Cc: Huang, Zhiteng; Tian, Kevin; Jiang, Yunhong; Li, Xin B
Subject: [Xen-devel] RE: [Question] Do we need to support devices that do not strictly follow the PCI-e specification?
Oh, I made some mistakes. I have just checked PCI-e 1.1 spec. It seems the definition of this capability structure is different with PCI-e 2.0. I will check more and find a solution.
From: Keir Fraser [mailto:keir.fraser@xxxxxxxxxxxxx]
Sent: 2008年10月9日 17:03
To: Shan, Haitao; xen-devel@xxxxxxxxxxxxxxxxxxx
Cc: Jiang, Yunhong; Li, Xin B; Tian, Kevin; Huang, Zhiteng
Subject: Re: [Question] Do we need to support devices that do not strictly follow the PCI-e specification?
On 9/10/08 09:28, "Shan, Haitao" <haitao.shan@xxxxxxxxx> wrote:
Hi, Keir,
When debugging recently, I found some devices that did not follow the PCI-e specification strictly. Below is an example.
From PCI-e spec, PCI-e capability occupies 0x3c bytes of configuration space. Unimplemented registers are reserved and hardwired to zero. But for device listed below, PCI-e capability should begin at 0x4C and end at 0x88. But this device implements MSI, VPD, MSI-X capabilities in the reserved spaces. Current code can not handle this.
My question is do we need to add hacks to handle such kinds of devices?
I thought PCI capability offsets could be dynamically determined? If so, or there are other means to easily determine actual capability offsets without requiring explicit device-quirk lists, we should employ those means.
-- Keir
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