[Xen-changelog] [xen-unstable] x86: Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1294221138 0
# Node ID 852d87e0480b4e813807bdef00e4d829850dc29a
# Parent  e635e6641c07ee2da66b16f46f45442c9a46821d
x86: Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

There is a new hardware feature, which lets system software to set
Energy Performance Preference. This is a opaque knob in the form of
IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance
Preference Hint.

The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer
to Intel Architectures Software Developer's Manual for more info.

Let dom0 tools to control it.

Signed-off-by: Wei Gang <gang.wei@xxxxxxxxx>
---
 xen/arch/x86/traps.c            |    1 +
 xen/include/asm-x86/msr-index.h |    1 +
 2 files changed, 2 insertions(+)

diff -r e635e6641c07 -r 852d87e0480b xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Wed Jan 05 09:50:21 2011 +0000
+++ b/xen/arch/x86/traps.c      Wed Jan 05 09:52:18 2011 +0000
@@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct 
                 goto fail;
             break;
         case MSR_IA32_THERM_CONTROL:
+        case MSR_IA32_ENERGY_PERF_BIAS:
             if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
                 goto fail;
             if ( (v->domain->domain_id != 0) || !v->domain->is_pinned )
diff -r e635e6641c07 -r 852d87e0480b xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Wed Jan 05 09:50:21 2011 +0000
+++ b/xen/include/asm-x86/msr-index.h   Wed Jan 05 09:52:18 2011 +0000
@@ -330,6 +330,7 @@
 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
 
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
+#define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
 
 /* Intel Model 6 */
 #define MSR_P6_EVNTSEL0                        0x00000186

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