# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID f4cef1aa25218c37c1ed94d00acaa2741abd0d1c
# Parent de5d2b9a9cfb2a01d6abe22ff51ae8b47c1d8865
Fix ASSERT failure caused by NX support code on x86_64
When turning on debug for x86_64, ASSERT(gpfn =3D=3D (gpfn & =
PGT_mfn_mask))
in __shadow_status will fail, this patch makes the NX support code
comply with this ASSERT.
NB: NX on PAE xen is not supported yet.
Signed-off-by: Xin Li <xin.b.li@xxxxxxxxx>
Signed-off-by: Jun Nakajima <jun.nakajima@xxxxxxxxx>
diff -r de5d2b9a9cfb -r f4cef1aa2521 xen/arch/x86/shadow.c
--- a/xen/arch/x86/shadow.c Tue Mar 14 15:00:16 2006
+++ b/xen/arch/x86/shadow.c Tue Mar 14 15:09:34 2006
@@ -3413,7 +3413,9 @@
l1_pgentry_t sl1e;
l1_pgentry_t old_sl1e;
l2_pgentry_t sl2e;
+#ifdef __x86_64__
u64 nx = 0;
+#endif
int put_ref_check = 0;
/* Check if gpfn is 2M aligned */
@@ -3428,7 +3430,9 @@
l2e_remove_flags(tmp_l2e, _PAGE_PSE);
if (l2e_get_flags(gl2e) & _PAGE_NX) {
l2e_remove_flags(tmp_l2e, _PAGE_NX);
- nx = 1ULL << 63;
+#ifdef __x86_64__
+ nx = PGT_high_mfn_nx;
+#endif
}
@@ -3436,7 +3440,11 @@
if ( !__shadow_get_l2e(v, va, &sl2e) )
sl2e = l2e_empty();
+#ifdef __x86_64__
l1_mfn = __shadow_status(d, start_gpfn | nx, PGT_fl1_shadow);
+#else
+ l1_mfn = __shadow_status(d, start_gpfn, PGT_fl1_shadow);
+#endif
/* Check the corresponding l2e */
if (l1_mfn) {
@@ -3454,7 +3462,11 @@
} else {
/* Allocate a new page as shadow page table if need */
gmfn = gmfn_to_mfn(d, start_gpfn);
+#ifdef __x86_64__
l1_mfn = alloc_shadow_page(d, start_gpfn | nx, gmfn, PGT_fl1_shadow);
+#else
+ l1_mfn = alloc_shadow_page(d, start_gpfn, gmfn, PGT_fl1_shadow);
+#endif
if (unlikely(!l1_mfn)) {
BUG();
}
diff -r de5d2b9a9cfb -r f4cef1aa2521 xen/include/asm-x86/mm.h
--- a/xen/include/asm-x86/mm.h Tue Mar 14 15:00:16 2006
+++ b/xen/include/asm-x86/mm.h Tue Mar 14 15:09:34 2006
@@ -98,8 +98,17 @@
/* 16-bit count of uses of this frame as its current type. */
#define PGT_count_mask ((1U<<16)-1)
+#ifdef __x86_64__
+#define PGT_high_mfn_shift 52
+#define PGT_high_mfn_mask (0x7ffUL << PGT_high_mfn_shift)
+#define PGT_mfn_mask (((1U<<23)-1) | PGT_high_mfn_mask)
+#define PGT_high_mfn_nx (0x800UL << PGT_high_mfn_shift)
+#else
/* 23-bit mfn mask for shadow types: good for up to 32GB RAM. */
#define PGT_mfn_mask ((1U<<23)-1)
+ /* NX for PAE xen is not supported yet */
+#define PGT_high_mfn_nx (1ULL << 63)
+#endif
#define PGT_score_shift 23
#define PGT_score_mask (((1U<<4)-1)<<PGT_score_shift)
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